Transcript High gain noise

Status of FATALIC and its MB
Tile Upgrade session during the AUW
Wednesday, 20 April 2016
François Vazeille on behalf of the Clermont-Ferrand team,
in particular
Roméo Bonnefoy, Romain Madar, Samuel Manen, Dominique Pallin, Laurent Royer and Sergey Senkin
 First phase of the noise study of the FATALIC readout
and impact on the design of the electronics cards
 Main Board-Daughter Board communication
 Impact of a wider integrator current range
 Sharing and pooling of the radiation tests
 Conclusion and prospect
1
First phase of the
noise study of the FATALIC readout
and impact on the design of the electronics cards
Summary of the talk at Weekly Tile Upgrade meeting (2016 March 23)
https://indico.cern.ch/event/505441/




TileCal specifications on the noise
Main objectives of FATALIC/noise
Systematic study
First conclusions
2
 TileCal specifications on the noise
- The rule: electronic noise = half the minimum charge of interest of 24 fC
corresponding to 1 photo-electron  12 fC for the design of FATALIC.
- This document is nowhere: it should be put on CDS.
- BUT: there was a mistake, the nominal PMT gain is 10 5 and not 1.5 10 5
 the electronic noise should reach 8 fC !
3
 Main objectives of FATALIC/noise
Main objectives of the FATALIC readout
1. An electronic noise  12 fC on the High Gain.
2. An external RMS noise < intrinsic noise of FATALIC.
3. A noise practically independent from the environment.
From the point 1 to the point 3,
these goals will be more and more difficult to reach.
… and why not to be better than 12 fC.
4
 Long systematic study, step by step, with improvements
FATALIC
1. Alone
2. Inside
PMT Block
3. Inside
FATALIC Test Bench
LV
HV
4. Inside Drawer
+ Main Board proto
5. Inside TileCal
at CERN
+ Main Board
+ Daughter Board
6. Inside Large box
at LPC
+ Main Board
+ Daughter Board 5
▪ There was a step O (Laurent Royer, TWEPP 2015 Lisbon)
intrinsic noise estimates from simulations of FATALIC alone.
High Gain noise:
2 ADC counts
ADC noise:
0.85 ADC count
ADC noise
Total noise (quadratic sum) = 2.2 ADC counts for the High Gain
or 5.5 fC.
6
▪ Experimental set-up (Example of Step 6):
PMT Block-Drawer-Main Board-Daughter Board inside a Big Test Box
+ LV/HV powers + laptop
FPGA memory of Main Board read out by USB interface
LV
HV
USB link
- Monitoring and data recording by LabVIEW on laptop.
- Readout supplied by LV regulators of Main Board.
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Gain selection (0 or 1)
Medium Gain
High Gain
RMS
FFT (Fast Fourier Transform)
▪
▪
▪
▪
Data: 5460 samples at 40 MHz.
Frequency spectra: 136.5 µs range  15 kHz to 20 MHz (Shannon theorem).
RMS accuracy: ~ 0.15 to 0.20 ADC count.
Charge calibration: 1 ADC count = (2.400.05) fC.
8
FATALIC
▪ Step 1: All-in-One alone
All-in-One#
13
15
23
21
Mean
Noise
2.7
3.0
3.0
2.7
2.850.17
(ADC counts)
- Measured intrinsic noise not far from simulation of 2.2 ADC counts.
- Equivalent noise in charge units: 6.840.43 fC.
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Signal
▪ Grounding aspects
PMT
PMT Block
Divider
High
Voltage
Drawer
FATALIC
In blue: Signal and/or digital information
In red : Grounding aspects
All-in-One
We played with all these objects
Main board
including the Black box (TileCal or box)
to minimize the noise level
Daughter
Board
Low
Voltage
Back End
electronics
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▪ Steps 2 and 3:
PMT Block alone
and inside FATALIC test box
PMT Block
Test Bench
▪Dramatic:
- Intrinsic noise increased about 4-5 times when connecting the PMT/Divider.
+ Noise peak at 2.6-2.7 MHz.
- Big sensitivity to the environment: position in the Test Box, cover or not…
HV
Test box
PMT
block
MB
LabVIEW
LV
11
Peak at 2.6-2.7 MHz
Zoom
Other peaks arose also at any moment
12
▪ Improvements from steps 4 to 6 (CERN, Clermont-Ferrand),
performed in the following order with a continuous noise decrease
1. A single ground on the active Dividers instead of 2.
2. Additional grounds connections on the active Dividers … but not too much.
3. Noise killers (Filters with 1 k resistor on HV power and return).
4. Well distributed metallic stand-off’s between cards or drawer body.
5. New connectors with more ground pins between Divider and All-in-One card.
6. Connections of the 4 pins of Dynode 8 instead of 1.
See the talk talk of the Weekly Tile Upgrade meeting (2016 March 23)
https://indico.cern.ch/event/505441/
showing the noise evolution.
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1. Single Divider ground
▪
▪
2 different grounds in the standard scheme:
Analog ground  FATALIC ground
With a 10  resistor connection
Power ground  HV ground
Not suited to an ASIC structure.
Replacements of the resistor by a direct connection
14
2. Additional ground wires
1. Standard Divider
Recto
The
best
1 single ground +
some ground wires
2. Modified Divider
3. Modified Divider + new grounds
Verso
15
4. Well distributed metallic stand-off’s
CERN
Drawer body/PMT Block/ MB/DB grounds at the same potential
16
5. New connectors on Divider/All-in-One cards
NEW
NEW17
- Previous scheme: 3 pins (Central: anode signal, Sides: ground).
- Changes: 7 pins (Central: anode signal, Others: ground).
6. New “discovery”: last dynode (D8) connected to 4 pins of socket,
but till now in ATLAS, only 1 (D8A) is used (Decoupled/ground.)
(D8 is roughly a dynamic ground/anode).
D8D
D8A
D8C
D8B
New active Divider
with:
- Single ground.
- Wire grounds.
- 4 D8 pins.
Modification: use of the 4 pins with 22 nF capacitors to the ground.
18
 Final results
 Effect of Noise killer: kills Peak at 2.6-2.7 MHz
Zoom
19
 Noise values in ADC counts then in fC
Gain
HV
off
HV
on
High
3.00
2.90
Medium
1.25
1.26
1.360.12
Low
1.14
1.15
On
1.370.11
High
2.8
2.9
Off
1.170.03
Medium
1.28
1.26
On
1.170.03
Low
1.15
1.15
Gain
HV
Mean
 RMS
High
Off
3.350.30
On
3.470.51
Off
Medium
Low
Means over
cards# 13, 15,21
-
In/out
Black Box
In
Out
Card# 21
PMT
Block
outside
Drawer
High
3.00
Medium
1.27
Low
1.14
PMT Block
alone
Card# 21
High gain noise in fC with HV off (On): 8.040.74 fC (8.331.24 fC ).
External noise: 1.76 ADC counts < intrinsic noise of 2.85 ADC counts.
Noise independent from the environment, with a low sensitivity to HV.
Rough estimates (from the noise levels of the 3 gains)
of the analog (Shaping) and digital (ADC) noise parts for HV off:
Analog: 3.3 ADC counts (Simulation: 2 ADC counts).
Digital : 1.1 ADC count (Simulation: 0.8 ADC count).
 Perhaps some margin of improvement of the analog noise.
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▪ First conclusions
- The 3 main noise objectives of the FATALIC read out are reached.
- The HV induced noise is negligible, within the uncertainties.
- Ground improvements are identified on the Dividers/All-in-One boards.
- Is it possible to improve again the electronic noise ?
Difficult because the noise is already very low,
but not impossible because of 3 reasons:
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1. The RMS values are calculated over the whole frequency spectra,
while only the high frequency noise should be considered (5.7-20 MHz).
Results on 3 All-in-One cards alone: noise reduction in % from
direct comparison of RMS values from HF and total frequency data (15 points)
Card #
13
15
21
Card alone
16.55.3
13.12.3
9.351.76
Simple mean
13.03.6
Weighted mean
11.11.6
A noise reduction of at least 11.1% is expected
 Noise close to 7 fC.
2. Cleaner modifications will be made on the new Divider and All-in-One.
3. A reduction of the analog noise could come from the following change
on All-in-One:
to reduce the distance between FATALIC and connector.
22
Main Board-Daughter Board communication
▪ Communication working
with Daughter Board V3
at 320 Mbits/s,
using VC707 and laptop.
it was a long and difficult task:
successful works of Roméo !
LPC
▪ Works during this expert week with Eduardo
- Test OK with Daughter Board V3.
- Use of the Daughter Board V4 with the new firmware: a short time to progress
 Data read but not in the right order.
 The debugging will go on at Clermont-Ferrand.
▪ As soon as V4 will be operational:
- Systematic tests are foreseen on a complete Drawer.
- Results will be given as soon as they will be significant.
23
Impact of a wider integrator current range
 Initial goals and specifications
 Additional goal and new specifications
 FATALIC approach
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 Initial goals and specifications
1. Cesium calibration of channels  Current integration over 10 ms*
*10 ms is the Cesium source transit time across a Tile.
2. Minimum Bias current  Current integration over 10 ms or more.
- Detector calibration at known Luminosity.
- LHC Luminosity stability at nominal value with a stable detector
from some 1033 to 1034 cm-2 s-1
 Currents from 0.1 nA to 1.2 µA.
 Additional goal and new specifications
from Ilya’s talk of last Tile upgrade week https://indico.cern.ch/event/491599/
- LHC Luminosity calibration at very low values  1030 cm-2 s-1
during the vdM calibrations of the LHC (van der Meer).
- HL-LHC Luminosity (5 times nominal value, aging aspects, etc.)
See also the ATLAS papers at 7 and 8 TeV:
Luminosity determination in pp collisions … (19th February 2016)
Submitted to EPJ C
 currents from 0.02 nA (A/B cells) to 100 µA (E cells).
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Strong impact on the electronics:
- Noise aspects at the lower limit of 0.02 nA.
- Saturation aspects at the highest limit of 100 µA.
 FATALIC approach
 What was foreseen with FATALIC before Ilya’s talk ?
To perform a digital sum of samples at 40 MHz.
 Digital sum realistic above a given current threshold (to fix)
with respect to the present electronic noise of 8 fC on every frequency,
without saturation problems at the highest values.
 Proposal of a possible complementary design for the low currents
 Current measurement over at least 10 ms,
with possibility of summing adjacent measurements.
 With an overlap with the pure digital approach.
 Fully implemented inside FATALIC:
with both the current integration stage and the ADC stage.
26
- In its principle, it is easy to perform current copies inside FATALIC:
at present, 3 copies are made  1 per Gain.
- Why not a fourth one  dedicated to the current integration ?
Simulation studies are in progress,
in particular the accessible range of low currents
27
Sharing and pooling of the radiation tests
 The organization is urgent because of several reasons:
- We must establish the list of components taken by each Institute.
- We have to design special cards supporting the tested components (20),
and also mechanical supports … depending from the chosen site.
- The funds must be spent this year at Clermont-Ferrand,
even though the tests will be made the next year.
 There is a critical point: the SEE tests of FPGA.
- SEE results depending from the code implemented at the irradiation time.
- If the code is different one day later … or 10 years later: obsolete conclusion.
- Same situation if the manufacturer modifies the chip (What is very likely !).
Moreover, the ATLAS radiation policy obliges us to test 20 chips !
 Schedules, works and cost problems difficult to solve.
 Discussion with Philippe Farthouat some weeks ago:
For the FPGA SEE tests, it will be enough to test some (1 or more) pieces,
repeated later before the final production for Phase II.
28
 Table of Clermont-Ferrand components (Sent on March 16)
11 active components to test from Main Board and All-on-One
with 5 of them (perhaps 6) are common withy Chicago
MB2v1 2015 common to FATALIC and QIE
MB2v2 2016 for FATALIC only
Grey: Removed or no required test
Red: Common with Chicago
Orange: Close to Chicago components
Identification
Manufacturer
Reference
Supplier
Nbr ver 2015
Nbr ver 2016
Remark
EP4CE30F23C7N
Altera
4
4
FPGA ALTERA *
EPCS4-SI8N ou EPCS16-SI8N
LTM 4619 EV
Altera
4 EPCS16
4 EPCS4
ALTERA memory
Diode schottky 6CWQ03FNTR
AD8030ARJZ
LTC 2360 ITS8
Oscillator 40 MHz -7C-40.000MBB-T
Transistor MOSFET SI7848BDP-T1-GE3
Linear Technology
Vishay Formely
2115887
Farnell
6
6
Regulator
1298453
Farnell
4
4
Power diode
AOP for voltage measurement
Analog Devices
2102502
Farnell
2
2
Linear Technology
TXC
1715090
Farnell
4
4
ADC only for temperature
1842044
Farnell
2
2
For test without CLK TTC 40 Mhz
Vishay Siliconix
2101455
Farnell
2
0
Linear Technology
LT 3759 EMSE#PBF-ND
2
0
Removed - 5V
Texas
1234907
Digikey
Farnell
12
0
Removed Buffer
Removed -5 V
LT 3759 EMSE
SN65LVDS389DBT
* For MB1 Chicago: EP4CE10F17C7N
All-in-One FATALIC
Identification
Reference
Supplier
Nbr: All-in-One FATALIC4b
FATALIC4 or 4b
2102502
LPC
Farnell
1
Analog Devices
2
AOP for voltage reference
MCP1726-1202E/SN
SN65LVDT390PW
Microchip
1851966
Farnell
1
Voltage reference 1.2 V
Texas
2335526
Farnell
1
LVDS Buffer towards LVTTL
LTC 2640AITS8-LZ12
Linear Technology
Texas
1715125
Farnell
1
DAC for injector
1494944
Farnell
1
Analog switch for injector
Manufacturer
Reference
Supplier
Nbr
Nbr : ver 2016
Remark
ZETEX
9526684
Farnell
3
3
Transistor
TSC
8150214
Farnell
3
3
Diode
FATALIC4b chip
AD8030ARJZ
TS5A23160DGSTG4
Maufacturer
LPC
Remark
Active Divider already radiation certified
Identification
FMMT458
TS4148 RXG
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Conclusion and prospect
 Crucial points in progress
▪ Good results on the Noise level on pulse analysis:
- Expected close to 7 fC, well below the initial specification of 12 fC,
and even below the strongest specification of 8 fC.
- Environmental noise < intrinsic noise.
- Noise independent of the environment
and with a low sensitivity to the applied HV.
▪ Grounding improvements on active Dividers and All-in-One cards.
▪ Main Board Daughter V3 communication operational, soon V4.
▪ Delivery of the list of components for radiation certification
for a sharing and pooling of tests.
30
 Started or foreseen works
▪ Production started on new Dividers and new All-in-One cards
for test beam.
▪ Preliminary study of a new current copy in FATALIC for calibration.
▪ Standard use (PPR) of the Daughter Board V4 with help of experts.
▪ Continuation of the FATALIC characterization .
▪ Building of a first dedicated Optimal Filtering.
▪ Phase II of the noise study on a complete Drawer
through the MB-DB communication
 Better statistics (12 channels).
 Same measurements
+ High Frequency noise measurements from pedestal widths.
+ Low Frequency noise for Calibration/Lumi purposes.
+ Comparison of Linear/Switching LV external power supplies
Comment: electronics already supplied by the regulators of the MB
which are switching power supplies.
31
With data through DB
10 V
LV
Standard Main Board
690 V
HV
1.5 m
/20 or 100 m
Daughter Board
HV Bus board with Noise killers
32
BACK UP
33
Distribution and frequency spectra for the 3 gains
High
Low
Medium
Medium
34