Transcript MUX-2011 - CERN Indico

A 20-b accelerometer-based
front-end for instrumentation
Enrico Sentieri – STMicroelectronics
Andrea Baschirotto – Univ. Milan-Bicocca
Microelectronics Users eXchange MUX-2011
CERN, June, 9th, 2011
Introduction





Introduction
Design Objectives
Noise Budget Partitioning
Architecture
ADC Architecture
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Sensor Accelerometers (1)
 Displacement accelerometers measure the displacement (x) of
a suspended proof mass (m) in response to an input
acceleration (a)
m
x = ´ ain
k
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Sensor Accelerometers (2)
 Displacement capacitive
sensors are widely used in
several systems
 Accelerometers
 Pressure sensors
 Microphone
 etc…
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Sensor Accelerometer (3)
 Most popular technique to measure the proof mass
displacement
  Capacitive Position Sensing
 Different Sensor-Capacitive-Bridge topologies
 Example:
 Two nominally equal-sized capacitor are formed between the electrically
conductive proof mass and stationary electrodes
 When the substrate undergoes acceleration
  the proof mass displaces from the nominal position
  capacitive half-bridge unbalacement
SenseP
Proof-Mass
SenseN
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Sensor Accelerometer Interface (1)
 Capacitors sense AC signals
  AC modulation sources for capacitive sensing
 The sensed signal is an Amplitude Modul. Signal
 The acceleration signal modulates a HF carrier
 To extract the envelopment
  The sensed signal need to be demodulated or sampled
 Accelerometer sensitivity ≈ modulation carrier amplitude
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Sensor Accelerometer Interface (2)
 SC Architectures are very popular
 MOS switches to connect the sensor and the circuit input.
 The thermal noise of MOS switches (kT/C noise)
 SC circuits are sample data systems
 It is not possible to insert an Anti-Alias filter between reading circuit
and sensor
  the input wide band noise is folded in base band
 SC have much higher noise
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Modulation/Demodulation
 Time Domain Signal Processing
Modulating signal
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Modulation/Demodulation
 Frequency Domain Signal Processing
DeModulating signal
ChAmp
Modulating signal
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Gain Error due to Op-Amp band limited (1)
 Modulation  the acceleration is transposed to the odd
harmonics frequencies of the Modulation signal
X 2 ´k +1
4 ´V0
1
=
´
π
2 ´ k +1
 The ChAmp transfer-function shapes the modulated signal
frequency spectrum
 High-frequency component attenuation
  The Demodulated signal amplitude is affected by ChAmp
Bandwidth
  Gain Error
 Gain error depends on process and temperature variations
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Gain Error due to opamp limited band (2)
Ideal Op-Amp (GBW=1GHz)
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Gain Error due to opamp limited band (3)
Ideal Op-Amp (GBW=1MHz)
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Mod/Dem-Freq vs. Power Consumption
 Higher Mod/Dem-Freq
  In CMOS circuit, the electronics low frequency flickernoise which often extends to low MHz
  Larger opamp Gain-Bandwidth
  Higher Power Consumption
  trade-off between performances and power
consumption
 Typically the Mod/Dem-Freq (fm) is from some tens of kHz
to MHz
  fm = 100kHz
13
Design Objectives





Introduction
Design Objectives
Noise Budget Partitioning
Architecture
ADC Architecture
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Design Objectives (1)
 Design a digitizing accelerometer interface that uses the full
bandwidth and dynamic range of the sensor
  The Sensor Signal Full-Scale is ±2G
  The total equivalent acceleration noise < 2.5μG
 sensor + electronic
SNR = 20 ´ log10 (
2G
1
´
) =115dB
2 2.5µG
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Design Objectives (2)
 Low power consumption
 Architecture choice
  Open-Loop Capacitive sensor Interface
 Interface Topology
  Charge Sensitive Amplifier with modulated input and
synchronously demodulated output
 The capacitive bridge is driven (modulated) by a squared
wave voltage
 Gain error (due to Sensor and Integrated Circuit process
variation) has to be compensated
 Bias Voltage Amplitude  10b resolution programmable
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Capacitive Sensor
 The Capacitive sensor
  fully-differential
 The bridge is driven
by a differential
signal a & b
 With an acceleration
 the capacitive
bridge is unbalanced
 a differential
charge is injected in
the pins A & B
A
Co
Cda1
Co
Cdb1
Co
Cda2
Co
Cdb2
Cp
B
Cp
a
b
Cload
Cload
Differential charge ≈ acceleration
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Capacitive Sensor Equivalent electrical Model
A
Sensor cap
Co fixed cap
Cdxxvariable cap
Co
Cda1
Co
Cdb1
Co
Cda2
Co
Cdb2
Cp
B
Cp
a
b
Cload
a&b  Modulating Sensor Pin
Cload
A&B  Reading Sensor Pin
Cda1 = Cdb2 = –Cda2 = –Cdb1 = SF · a
SF : Scale Factor [F/g]
a: acceleration [g]
Sensor Topologies:
Jiangfeng Wu. “Sensing and
Control Electronics for LowMass Low-Capacitance
MEMS Accelerometers”,
Department of Electrical and
Computer Engineering,
Carnegie Mellon
University,Spring 2002.
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Capacitive Sensor Parameters
 Sensor Input and Interconnection Capacitance
  Cp=12pF
 Cload=20pF
 Sensor cap
 Co=1pF
 Scale Factor
  SF = 300fF/G
 Sensor Dynamic Range
  ±2G  S=2G
 Sensor Noise Density
  asn=100nG/sqrt(Hz)
 Sensor Bandwidth
  BW=300Hz
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Ideal Sensor Accelerometer Interface
CAPACITIVE SENSOR
A
Cf
B
Cf
Co
Cda1
Cdb1
Cdb2
Cda2
Cl
Co
ADC
Co
Cp
Cl
Co
Cp
Charge
Amplifier
a
Demux
AAF
b
DAC
Drivers
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Technology Choice(1)
 The technology choice driven by:
 Performance
 Cost
 Process Maturity
 Analog Option Required
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Technology Choice (2)
 Standard CMOS technology with double thick oxide
 A rough system analysis
  more than 90% device area is used for analog blocks
  No need to use technology with high level of integration density
  The technology choice is driven by analog requirement
 A Mature technology with two different thick oxide MOS has
been selected:
 70Å (3.3V gate, 0.350μm minimum channel length)
 120Å (5.0V gate, 0.500μm minimum channel length)
 The 5.0V MOS slower and noisier than 3.3V MOS
 Two power supply domains (5.0V & 3.3V) are available
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Technology Choice (3)
 Resistors
 Linear Resistor (Doped-Poly resistor)
 Diffused Resistor
 poor linearity
 no flicker noise compared to the poly resistor
 HIPO (High resistance poly) resistor
 higher sheet resistance compared to poly resistor.
 extra mask  higher cost
 Capacitor
 High-linearity caps required for the Charge Amplifier feedback capacitor and
ADC (Switched Capacitor)  Metal to metal capacitor is the best choice
 MIM (Metal Insulator Metal)
 Thin oxide  High density level
 Extra Masks  Higher Cost
 Fringed Capacitor
 Lower density
 No extra mask
23
Noise Budget Partitioning





Introduction
Design Objectives
Noise Budget Partitioning
Architecture
ADC Architecture
24
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Noise Budget Partitioning (1)
 Starting from high level specifications
  define the specification for each
blocks of the system
  identify critical blocks
  roughly definition of a suitable
architecture of each block
 Simplifications
 This preliminary analysis should be
done not considering mod/dem effects
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Noise Budget Partitioning (2)
 The Noise Budget partitioning is an iterative design process
 Some design specifications are defined based on preliminary
analysis/assumptions
  the required performances for each block are evaluated
 in case of any issue, the assumptions will be modified
 It’s quite impossible, at the first run, to identify all the critical
design parameter
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Noise Budget Partitioning (3)
 Target: Total noise  an_rms= 2.5µG
 Two different main Noise contributors:
 Sensor Noise (Brownian Noise)  asn_rms
 Electronic Noise  aen_rms
 Quantization Noise, Thermal Noise, & Flicker Noise
 Sensor Noise (asn_rms):
asn_rms = asn ´ BW =100nG/ Hz ´ 300Hz =1.73 µG
 Electronic Noise  Equivalent Acceleration noise is
evaluated to match the design Objectives:
2
2
aen_rms = an_rms
- asn_rms
= 1.81µG
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Noise Budget Partitioning
 Assuming no-noise sensor
1.8µV
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Noise Budget Partitioning (4)
 SNR due to the only electronic Noise evaluated at Sensor
level:
SNRe = 20 ´ log10 (
S
2
´
1
aen_rms
) =117.9dB
  First design specification,
 the SNR @ADC-output > 117.9dB
  ADC resolution has to be:
ENOB ADC >
SNRe -1.76
=19.3bit
6.02
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ADC Performances (1)
 ADC resolution >19.3 bit
 SC-SD Architecture
  the only one to satisfy this challenging design
specifications.
 Oversampled ADC architecture  Relaxed the AntiAlias Filer requirements specification
 The small signal bandwidth
 Critical opamp flicker-noise
  the ADC with Correlated Double Sampling or
Chopper Stabilization technique
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ADC Performances (2)
 Which Power Supply?
 ADC under 5V supply domain
  higher reference voltage compared to 3.3V supply domain
  Sample capacitor reduction (less area) and/or reduce the
Oversampling Ratio (smaller opamp bandwidth)
Vsignal µV ref
V noise
K b ´T
µ
Cs ´ OR
Vref: ADC reference Voltage
Kb: Boltzmann Constant
T: Temperature
Cs: Sampling Capacitor
OR: Oversampling Ratio
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ADC Performances (3)
 Which Power Supply?
 5.0V MOS have higher 1/f noise than 3.3V MOS
 Increased oxide thickness  Increased trap number in the
silicon oxide interface.
 If the ADC is designed under 5.0V domain
  The Charge-Amplifier to be designed under the same
supply domain to use all the available ADC dynamic range
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ADC Performances (4)
 Both solutions have some advantages (larger signal @5V) and
some drawbacks (larger 1/f noise @5V)
 The best compromise performance vs. power consumption
has been achieved supplying the ADC and Charge Amplifier
at 3.3V
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ADC Performances (5)
Assumptions:
 ADC Differential Reference Voltage  2.5Vpeak
 Possible under 3.3V domain
 Maximum ADC Input signal  2.0Vpeak
 To avoid Modulator Saturation issue
 ~2dB of margin
 ADC resolution required 20 bit
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ADC Performances (6)
 Total Noise at ADC output
Vn
@ADCoutput
S in_ADC
=
2
max
´10
SNRe
20
=
2
2
´10
117.9
20
=1.8 µV
 ADC Noise
 Assuming dominant quantization noise
VnADC =
LSB
12
=
V in_ADC
max
2 (nbit -1)
1
2
1
´
= 19 ´
=1.1 µV
12 2
12
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Biasing and Reading Noise partitioning
2
VnBiasRead = Vn2_@ ADCout -VnADC
=1.42 µV
 The system is divided in to two different macro blocks:
 Reading (Charge Amplifier and AAF)
 Biasing (DAC and Driver)
Noise Biasing/Noise Reading
3/1
2/1
1/1
1/2
1/3
Noise Biasing
VnBias
1.35μV
1.27μV
1μV
0.63μV
0.45μV
Noise Reading
VnRead
0.45μV
0.63μV
1μV
1.27μV
1.35μV
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Noise Budget Partitioning
 Assuming no-noise sensor
1.8µVrms
1.1µVrms
1.4µVrms
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Sensor Transfer Function
Cf
A
Co
Cda1
Co
Cdb1
Cp
Va
Co
Vadc
Vb
Cda2
Co
Cdb2
B
Cp
Vs @ ADCinput =Va ´
Cf
Charge Amplifier
Cda1
C
C
C
C
+V b ´ db1 -Va ´ da2 -V b ´ db2 = 2 ´ d ´ (Va -V b )
Cf
Cf
Cf
Cf
Cf
SF ´ a
Vs @ ADCinput = 2 ´
´ V bias
Cf
Vbias is the differential Voltage applied to the sensor
Vs @ ADCInput
a
V bias
=2 ´
´ SF
Cf
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Biasing Noise Gain
A
Co
Cda1
Co
Cf
Cdb1
Cp
Vna
Co
Vnadc
Vnb
Cda2
Co
Cdb2
B
Cp
2
2
V na@ADCinput
V na@ADCinput
Cf
Charge Amplifier
2
æ 2 ´C ö
æ 2 ´C ö
2
2
d
d
=V na ´ ç
÷ +V nb ´ ç
÷
è Cf ø
è Cf ø
2 ·Cd
2 ´ SF ´ a
=
´ V na2 +V nb2 =
· V na2 +V nb2
Cf
Cf
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Charge Amplifier Noise Gain
Cf
Co
Cd
Co
-Cd
Vnop
Cp
-
Vnadc
Cin
+
æ 2 ·C + C + C ö
o
p
in
÷
V nop@ADCinput =V nop ´ çç1 +
÷
C
è
ø
f
2 ·Co + C p + C in
NGChAmp =1 +
Cf
Cin Charge Amplifier Input Cap
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Biasing Voltage (1)
Vs @ ADCInput
a
V
= 2 ´ bias ´ SF
Cf
VnBias@ADCInput
NGChAmp =1 +
2 ·Co + C p + Cin
Cf
2 ´ SF ´ a
=
· V na2 +V nb2
Cf
 To maximize the ADC input  two possibilities:
 Increase the Bias Voltage
 Decrease the ChAmp feedback cap (Cf)
  Increase the Charge Amplifier Gain
 Cf  the (ChAmp & BiasCircuit ) ADC input noise
  No effect on the overall SNR
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Biasing Voltage (2)
 To optimize SNR
  Vbias has to be maximized
  The Sensor Drivers has to be realized under 5.0V
Supply Domain
 Considering Supply Variation & Driver Output MOS headroom
 Vbias=4.5V
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Charge Amplifier Feedback capacitor
  Vbias=4.5V
 The feedback cap (Cf) is evaluated to maximize ADC DR when
the maximum acceleration (amax) is applied to the sensor
V ADC
SF ´ a
=2 ´
´V bias
Cf
Cf = 2 ´ SF ´ amax ´
V bias
4.5V
= 2 ´ 300fF/G ´ 2G ´
= 2.7pF
V ADCmax
2V
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Biasing and Reading Noise partitioning (2)
 Read-out noise  Charge Amplifier noise
NGChAmp =1 +
2 ´ Co + C p + C in
Cf
>1 +
2 ´ Co + C p
Cf
2 +12
= 1+
= 6.2
2.7
 The Charge Amplifier Input Noise is amplified
 Bias Noise Gain
NGBiasmax

DCmax 2 ´ SF ´ amax 2 ´ 300fF/G ´ 2G
=
=
=
= 0.44
Cf
Cf
2.7pF
The Bias Input Noise is amplified
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Biasing and Reading Noise partitioning (3)
 Reading Noise is more critical than Biasing Noise due to Charge
Amplifier Noise Gain
 Strategy: Increasing the Reading Noise Budget compared to the
Biasing Noise Budget
 1/2 may be the best compromise to increase the reading Noise Budget
 1/3 small improvement for Reading and bigger worsening for the Biasing
Noise Budget
Noise Biasing/Noise Reading
3/1
2/1
1/1
1/2
1/3
Noise Biasing
VnBias
1.35μV
1.27μV
1μV
0.63μV
0.45μV
Noise Reading
VnRead
0.45μV
0.63μV
1μV
1.27μV
1.35μV
Vn Read @ ADCInput =1.27µV
VnBias @ ADCInput = 0.63 µV
Þ
V nBias @ DriverOutput =
0.63 µV
0.44
=1.43µV
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Noise Budget Partitioning
 Assuming no-noise sensor
1.8µVrms
1.3µVrms
0.63µVrms
1.1µVrms
1.4µVrms
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Noise Budget Partitioning Conclusion
 Starting from the high level system specifications
  a preliminary noise breakdown
 To descend the hierarchy, it is necessary to define the
architecture of each block
  Next step  defining the circuits architecture and their
noise budget
 It is mandatory to take into account the mod/dem effects
47
Architecture





Introduction
Design Objectives
Noise Budget Partitioning
Architecture
ADC Architecture
48
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Charge Amplifier
 Assuming no-noise sensor
1.8µVrms
1.3µVrms
0.63µVrms
1.1µVrms
1.4µVrms
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Charge Amplifier (1)
 Charge Amplifier needs a opamp input DC polarization
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Charge Amplifier (2)
VChAmp
Vs
R f ´ Cs ´ s
=
1 + R f ´ Cf ´ s
 The Charge Amplifier Signal is Amplitude Modulated
 Carrier frequency  fm
 To reduce the Charge Amplifier gain error
 The pole frequency has to be lower than modulation frequency
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Charge Amplifier (3)
V n2 = 4 ´ k b ´T ´ R f
V nChAmp
Vn
=
1 + Cf ´ R f ´ s
V nChAmp @f=f
m
2 ´ 4 ´ k b ´T ´ R f
2 ´ k b ´T
=
»
2
1 + (2 ´ π ´ f m ´ R f ´ C f )
R f ´ (π ´ f m ´ C f ) 2
 Rf   Output Noise density (due to Rf) 
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Charge Amplifier (4)
 The noise spec  VnRead = 1.27μV
 Assumption:
 Rf-Noise ≈ 1/3 of the to Total Noise (negligible effect in the
noise power budget)
 The ChAmp Output Noise density due to feedback resistor is:
1.27mV
= 24nV / Hz
3 ´ 300
 Assumption: Modulation frequency fm=100kHz
2 ´ k b ´T
Rf ³ 2
= 20MΩ
2
V n _ChAmp @ f =f ´ (π ´ f m ´ C f )
m
f pole =
1
= 3kHz << f m
2 ´ π ´ R f ´ Cf
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Charge Amplifier (5)
 Large Rf’s
 are difficult to be integrated in standard CMOS process
 require large Area
 Switched Capacitor
 MOS operating in triode
 Integrated Resistor
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Charge Amplifier (6)
 Switched Capacitor capacitance sensing
“Correlated Double Sampling in Capacitive Position Sensing Circuits for Micromachined Applications”
Wongkomet, N.; Boser, B.E.;1998
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Charge Amplifier (7)
 Switched Capacitor capacitance sensing with CDS
“Correlated Double Sampling in Capacitive Position Sensing Circuits for Micromachined Applications”
Wongkomet, N.; Boser, B.E.;1998
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Charge Amplifier (8)
 MOS operating in Triode region
(W/L)1
R=
´ N ´ R ref
(W/L)2
“Single-Chip Surface Micromachined Integrated Gyroscope with 50º/h Allan Deviation”
J.A. green, S. J. Sherman, J.F. Chang and S.R. Lewis - 2002
 Good operation with small (Vo-Vi) to keep M2 in triode
  Same ChAmp Input and Output
  This solution is mainly used when a pre-Amplifier is
inserted after the Charge Amplifier
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Charge Amplifier (9)
 Integrated Resistor




 No Noise Folding
 Better Linearity/No dynamic limitation
 Better Noise Performance
 Huge Area increments
 Roughly Area Estimation
 Doped Poly Typical Rs(/sq)=300  area for 2x 20M & W=1μm
A=
2 ´ 20MΩ
= 0.13mm 2
300
 HIPO Rs(/sq)=1000  area for 2x 20M & W=1μm
A=
2 ´ 20MΩ
= 0.04mm 2
1000
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Charge Amplifier (10)
 Diffused Resistor have Rs higher or equal to HIPO resistor
  Standard process (no extra mask)
  Linearity Issue
  Junction Leakage at the high Impedance Input of the
Charge Amplifier
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Charge Amplifier (11)
 The choice between HIPO and doped Poly depends on cost
evaluation (mask/process vs. area)
 The real area used for the feedback resistor is higher than first
roughly estimation
 Distance between modules
 Active area density
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Charge Amplifier (12)
 ChAmp opamp
 Output swing & Anti-Alias Filter Resistive Load
  Two-Stage topology
 High current during the carrier rising/falling edge
  Class-AB output stage
 Overall gain error reduction
  Closed-Loop gain-gandwidth > 10x fm
 ChAmp feedback factor ≈ 1/NGChAmp= 1/6
 Opamp noise is chopped
  Thermal noise dominates
  Thermal noise reduction
 Large differential pairs and current generator MOS
  high parasitic capacitor
  stability Issue
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Charge Amplifier (13)
 Usually LN  PMOS input differential pair (PMOS have lower 1/f noise
than NMOS)
 Recent technologies have small difference between P-Ch and N-Ch
flicker noise  Op-Amp with N-Ch differential pair can achieve better
Noise performance
 The advantages of N-Ch differential pairs:
 Higher gm  Lower thermal noise
 Higher rejection of the P-Ch current generator Noise.
 Opamp noise is
choppered
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Charge Amplifier (14)
 Low Noise circuits design
 large transistor
  large channel width and MOS area
  thermal and 1/f noise reduction
 In case of capacitive sensing
NGChAmp =1 +
2 ´ Co + C p + Cin
Cf
 Large Transistor
  Large gate capacitance
 Increased Charge Amplifier Noise Gain
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Charge Amplifier (15)
Cf
Co
Cd
Co
Vnop
Cp
-Cd
-
Vnadc
Cin
+
 For dominant thermal noise (chopper)
Cin £ Csensor + Cint erconnect
 Minimum noise for
NGChAmp =1 +
2 ´ Co + C p
V nRead@ADCInput
NGChAmp ´ BW
Cf
=
= 6.2
1.27µV
6.2 ´ 300Hz
» 11nV / Hz
64
MUX-2011
Charge Amplifier (16)
 This rough result is useful only to understand the challenge of
the Charge Amplifier opamp design
  11nV/√Hz is an aggressive input noise target
 To reduce the noise
 Sol1  mod/dem frequency (fm) increase
  fm > opamp flicker corner frequency
  higher power consumption (the Mod/Dem frequency
effects all the circuits specifications)
 Complexity in circuits Implementation
 Sol2  chopper opamp
65
MUX-2011
Charge Amplifier (17)
 The opamp 1/f noise is
modulated by the Choppered
square wave at frequency f1
(Odd harmonics)
 The opamp modulated output
signal is down converted by the
demodulation clock (fdem)
 F1 defined avoid that its odd
harmonics are down converted
in base band by the
demodulation square wave
 Ex.: f1=1000kHz & fdem=100kHz
66
MUX-2011
Charge Amplifier (18)
First Stage of the Chopper Charge Amplifier Op-Amp
67
MUX-2011
Charge Amplifier (19)
 Both solutions (Choppered and CT) have been designed and
compared.
 CT solution performs the best results with the in term of:




Power consumption
Performances
Linearity
Development time
 Op-Amp specification:
 GBW ≈ 10MHz
 Input referred Noise ≈ 11nV/√Hz
 Current Consumption ≈ 2.2mA  [email protected]
68
MUX-2011
Anti-Alias Filter (1)
 Large ADC Over Sampling Ratio
  One single pole Filter is enough to reduce the folding
noise issue
 The Reading Block Noise budget is mainly used by the Charge
Amplifier (High Complexity).
 If active solution is implemented the AAF Op-Amp needs
Chopper Stabilization technique in order to remove the flicker
Noise
 Passive Filter with external capacitor solution is widely used in
very high performance standalone ADC.
69
MUX-2011
Anti-Alias Filter (2)
 The value of the AAF resistor is designed in order to have an
attenuation of 0.4dB between the Dem. output and the ADC
Input
Fs=6MHz, Cs=10pF  Req=17M
Raaf=800
70
MUX-2011
Anti-Alias Filter (3)
 The AAF noise voltage:
vn
Raaf
= 4 ´ k b ´T ´ Raaf ´ BW = 65nV
Negligible
Cext=20nF >> Cs
Cut-Off frequency: 10kHz < Modulation frequency
Attenuation at the ADC sampling frequency: -56dB
71
MUX-2011
Anti-Alias Filter (4)
Passive Anti-Alias Filter solution






 Simple
 Less Risk compared with Active solution
 Noiseless
 No power consumption
 Requires external capacitors
 Gain Error
72
MUX-2011
Bias Circuit
 Assuming no-noise sensor
1.8µVrms
1.3µVrms
0.63µVrms
1.1µVrms
1.4µVrms
73
MUX-2011
Bias Circuits
 Low Power/Low Noise Application  Reduce no. of circuits
 The Biasing circuit is divided in two blocks
 DAC that is used to set the amplitude of the Carrier
 Driver feeds the Sensor and Buffer the DAC output
 High Impedance input Driver
 Two possible Implementations:
 DAC dynamic Range 4.5V
 Driver  Buffer
  Rail-to-Rail Input Stage Op-Amp
 DAC dynamic Range 2.5V (as ADC)
 Driver  Non-Inverter gain configuration
  The DAC and Driver Input Noises are amplified
74
MUX-2011
Bias circuit / Rail-to-Rail Input Stage (1)
75
MUX-2011
Bias circuit / Rail-to-Rail Input Stage (2)
 Rail-to-Rail Input stage critical point  distortion due to
different offset of the P-ch and N-ch diff-pairs
 A squared wave is added to the carrier, its amplitude is equal
to the difference between the N-ch and P-Ch differential pairs
Offset.
 The carrier amplitude is effected by Offset Issue and it
depends on DAC setting  equivalent to an INL issue
76
MUX-2011
Bias circuit / Rail-to-Rail Input Stage (3)
 INL problem reduced increasing the MOS sizes to be < DAC INL
 Additional problem  the diff-pair differential Flicker Noise is
modulated
 The power of the modulated Flicker Noise is equal to the sum
of P-Ch and N-Ch differential pairs Flicker Noise power
 The Driver Modulated Flicker Noise is demodulated in base
band by the Demodulator and so it appears at ADC output
77
MUX-2011
Bias circuit / Non Inverting Amplifier (1)
Fully Differential Difference Amplifier




 No extra Pole due to current generator
 Good CMRR
 More design Complexity
 Needs Common Mode Feedback Circuit
78
MUX-2011
Bias circuit / Non-Inverting Amplifier (2)
 Single Ended opamp
  Simple Architecture
  Less power (No CMFB)
  Extra pole due to
differential to Single-Ended
MOS diode
  No Common Mode
Rejection (the Common
Mode and Differential signals
are Amplified)
79
MUX-2011
Bias circuit / DAC Architecture
Reference
DATAIN
10

10 Bit
DAC
MOD_CLK
Dacp
DriveIn_p
Dacn
DriveIn_n
Differential DAC inserted before the Modulator
  Static DAC.
  DAC noise is not Choppered (Inserted before Modulator).

Two possible topologies:
 Current Steering

Resistive DAC Array (Poly Resistor)
Poly Resistor Flicker Noise is lower than MOS flicker Noise
80
MUX-2011
Rp1pp (p+poly res) Flicker/Thermal Noise evaluation (1)

Flicker noise (pink noise) is present in polysilicon resistor with thermal noise.

It depends on bias voltage, area and frequency as shown below:

Vn² Vbias²/ (W.L.f)  flicker noise increases as bias voltage increases
Ideal thermal noise for 1k  √[4*1.38e-23·300·103]= 4.07nV/√Hz

Total noise simulation graph of 1k, Rp1pp resistor with 1uA ( ∆V = 1mv)
1V
1 kOhm
O/p for
noise
1µA
MUX-2011
Rp1pp (p+poly res) Flicker/Thermal Noise evaluation (2)

Total noise simulation of 1kΩ, Rp1pp resistor with 100uA ( ∆V=0.1V)
1V
Note:: Vn @ 250Khz is 4.108v/rtHz
1 kOhm
O/p for
noise
100µA
MUX-2011
MDAC Architecture
 DAC Flicker Noise Reduction
  Increase the dimension of the Resistor (Huge Impact on device area)
  Move the Modulation before the DAC  MDAC Architecture
MOD_CLK
VREFP
VREFP
VREFN
VREFN
VREFN
REFP
REFN
VREFP
DriveIn_p
DATAIN
10
10 Bit DriveIn_n
MDAC
83
MUX-2011
MDAC topology (1)
 10 Bit Differential MDAC Single Resistor String
solution:
 2*1024 resistors
 2*1024 switches
  Good linearity
  Too Small value of the Resistor Module
  Huge Number of switches
 Area
 Parasitic Capacitor
84
MUX-2011
MDAC topology (2)
10 Bit Differential MDAC Double resistors
(Segmented)String Array
85
MUX-2011
MDAC topology (3)
 10 Bit Differential MDAC Double Resistor String
Array solution:
 2*64 resistor
 2*64 switches
  Worse linearity
  Bigger Resistor Module
  Reduced Number of switches
86
MUX-2011
Driver Feedback resistor (1)
 The squared wave current flowing in the feedback resistor
modulates the flicker Noise of the P-Poly resistance
 The resistor flicker noise is folded in base band by the
demodulator
87
MUX-2011
Driver Feedback resistor (2)
Ideal Op-Amp
Ideal FeedBack resistor
Steady state Noise Analysis
Ideal Op-Amp
Poly Resistor
88
MUX-2011
Driver Feedback resistor (3)
 Solutions
 Increase the value of the feedback resistor
  maximum current reduction
  thermal noise increase
 Increase the feedback resistor area
  flicker noise reduction
  parasitic capacitor increase
  stability issue and/or reduced closed loop bandwidth
 Use Diffused resistor, with negligible flicker noise
  Linearity Issue
89
MUX-2011
Driver Operational Amplifier (1)
 Output Dynamic range and Resistive feedback
  Two stage operational Amplifier
 Low power
  Class AB Output Stage
 Input Voltage Range [125mV-to-2.625V]
  P-Ch Input stage and supplied under 5V domain
 Output Voltage Range [125mV-to-4.625V]
90
MUX-2011
Driver Operational Amplifier (2)
91
MUX-2011
Driver Operational Amplifier (3)
 The Input Voltage Range is compatible with 3.3V MOS
 3VMOS better noise performance than 5VMOS
  (M1, M2, M3, M4, M5 and M6 are 3.3V MOS)
 Ahuja compensation
  move the output pole at higher frequency
 Output series resistor to Sensor Capacitive load adds a zero
that help stability
92
MUX-2011
Noise Budget Partitioning
 Assuming no-noise sensor
1.8µVrms
0.44
0.8µVrms
1.8
1.3µVrms
1.43µVrms 0.63µVrms
1.1µVrms
1.4µVrms
93
MUX-2011
Biasing Circuit Design (1)
 Driver Gain GDriver=4.5V/2.5V=1.8
0.63µV
VnBias@DriverOutput =
=1.43 µVrms
0.44
V nBias@DriverOutput 1.43 µV rms
VnBias@DriverInput =
=
= 0 .79 µV rms
GDriver
1.8
 The noise budget is equally divided between MDAC & Drivers
VnMDAC =V nDrivers =
VnBias@DriverInput
2
= 0 .56 µV rms
 Two equal single-ended drivers are used
VnDriver =
V nDrivers
2
= 0.4 µV rms
94
MUX-2011
Biasing Circuit Design (2)
 Driver Noise Contributors
 Opamp
 Feedback resistor
 The Driver Noise budget is equally divided between opamp
and Feedback resistor contributors (No optimization)
VnDriver 0.4 µV
Only thermal noise
VnD_OP =VnD_RFB =
=
= 0.28 µV
æVn
ç D_RFB
ç
è BW
2
2
2
VnD_OP VnD_RFB 0.28µV
=
=
= 16nV / Hz
BW
BW
300
ö
4 ´ k b ´T ´ R 2
÷ =
÷
æ R ö
ø
ç1 + 2 ÷
R1 ø
è
R 2 = 28kΩ Þ R1 = 35kΩ
Ifb|max = 70 µA
95
MUX-2011
Biasing Circuit Design (3)
 Opamp design is mainly driven by gain bandwidth requirement
 GBW=4MHz
 Input referred Noise density= 28nV/√Hz
 Driver Current Consumption =300uA
 Total Driver Current consumption
 Itot=300μA+300μA+72μA=672μA
 Ptot=3.4mW
96
MUX-2011
Biasing Circuit Design (4)
 DAC Noise three contributors:
 Reference Voltage
 Resistor Array
 Switches
 The Noise Budget is equally divided
between the three contributors
 No optimization
 The single ended contributors are:
VnMDAC
6
=
0.56 µV
6
= 0.22 µV Þ13nV/
Hz
97
MUX-2011
Biasing Circuit Design (5)
 The relationship between Coarse and Fine resistor depends
on DAC Linearity requirements
2
 Ex.: Rf=4·Rc
13nV/ Hz = 4 ´ K b ´T ´ 8 ´ (Rc + R f )
(
)
Rc = 255W
I DAC =
R f = 1020W
V ref
= 153m A
32 ´ Rc ´ 2
98
MUX-2011
Biasing Circuit Design (6)
 Power consumption reduction
  two external caps filter the noise coming from VREF
 The DAC reference opamp is choppered
 Static opamp
  Low power consumption (<100µA per-buffers)
99
MUX-2011
Power Consumption
Current
Consumption
[ μA ]
Supply Voltage
[V]
Power
Consumption
[ mW ]
2200
3.3
7.3
0
3.3
0
Drivers
672
5.0
3.4
Differential MDAC
353
3.3
1.16
Charge Amplifier
Anti-Alias Filter
100
MUX-2011
Driver Noise vs. DAC Output Slope (1)
 Output steps would have to be as more ideal as possible
101
MUX-2011
Driver Noise vs. DAC Output Slope (2)
 Tal current generator noise is
modulated by the diff-pair unbalancement in slew-rate
conditions
  Additional noise
102
MUX-2011
Driver Noise vs. DAC Output Slope (3)
 Tail current generator modulated noise reduction
 Sol1  Increase Op-Amp Gain Bandwidth
  Increase power consumption
 Sol2 Decrease DAC Output Signal Slope
  Increase Gain error (The effect is equivalent to reduce the
Carrier Amplitude)
  To match the maximum ADC dynamic range the Charge
Amplifier gain has to be increased
 Trade off GBW vs. Slope  Power vs. Noise
103
ADC Architecture





Introduction
Design Objectives
Noise Budget Partitioning
Architecture
ADC Architecture
104
MUX-2011
20b 250Hz ADC
 Sigma-Delta is the only possible 20b ADC solution
 No matching requirement
 Oversampling requirement (easy to be performed at small
signal bandwidth)
105
MUX-2011
20b 250Hz Sigma-Delta ADC
 Overall Specs







ADC Resolution:
THD
Bandwidth
Output rate
Anti Aliasing Filter
Supply Voltage
Area
> 20 bit (SNR >123 dB)
< -90 dB
1Hz-250Hz
500 Sps
External
3.3V
< 3.5 mm^2
106
MUX-2011
20b 250Hz Sigma-Delta ADC
 Noise Budget calculation
 Reference Voltage: 2.5V
 Input Amplitude: 4Vpp (1.4Vrms)
 For 125dB-SNR  Total Noise ≈ 700 fV2
107
MUX-2011
20b 250Hz Sigma-Delta ADC
 Noise Budget calculation
 For 125dB-SNR  Total Noise ≈
 Noise Budget
 Opamp Noise after chopper
 kT/C Noise
 250 fV2 < kT/(Cs·OSR)
 Reference Noise
 Qnoise + Other noise
700 fV2
150 fV2
250 fV2
200 fV2
< 50fV2

  Equivalent SNR (considering only Qnoise) = 136 dB
  MATLAB SNR requirement > 136 dB
108
MUX-2011
20b 250Hz Sigma-Delta ADC
 Sampling frequency choice
 Low sampling frequency
 Quantization noise
 Low OSR  low resolution
  high order
 QN is not the key limitation !!!
kT
 Thermal noise
C
2·Fb
kT
N inband = s =
·
 Low OSR  large in-band noise
OSR
Fs
Cs
 For a given DR  Larger CS  higher Power
 High sampling frequency
 Smaller sampling period
 Larger opamp bandwidth spec  higher power
 Larger slew-rate  higher power
109
MUX-2011
20b 250Hz Sigma-Delta ADC
 Sampling frequency choice
 Trade-off choice
  OSR= 8.192
  Fs = 250 x 2 x 8.192 = 4.096 MHz
  Ninband2=(kT/CS)/OSR
  CS = kT / (Ninband2·OSR) = 10pF
110
MUX-2011
20b 250Hz Sigma-Delta ADC – Topology Choice
 Single-bit 2+2-MASH
  No DAC cap mismatch sensitivity
  Cap mismatch sensitivity in the noise canceling
network
  Large Slew-rate
requirements
  Simple feedback DAC
network
 Stability !!!
111
MUX-2011
20b 250Hz Sigma-Delta ADC – Topology Choice
 2nd-order FeedForward single-loop
 No signal in P & R
 Maximum opamp output swing  Quantizer LSB
 Useful for multi-bit quantizer
  Small integrator output swing
112
MUX-2011
20b 250Hz Sigma-Delta ADC – Topology Choice
 3-bit 2nd-order FeedForward single-loop
  DAC cap mismatch sensitivity
  No Cap mismatch sensitivity in the noise canceling
network
  No Finite opamp sensitivity in the noise canceling
network
  Reduced Slew-rate requirements
  Feedback DAC network with DEM
113
MUX-2011
20b 250Hz Sigma-Delta ADC – Topology Choice
 Silva’s Topology 
  Two input branches
 Lower load for the
previous stage
  Single DAC
 Nys’s Topology
  Three input branches
 Higher load for the
previous stage
  Two DACs
114
MUX-2011
20b 250Hz Sigma-Delta ADC – Topology Choice
 FF Topology
 Amplitude swing @ Integrator outputs
 Output swing < VFS/2  relaxed opamp output swing
  Low Power Consumption
115
MUX-2011
20b 250Hz Sigma-Delta ADC – Topology Choice
 FF Topology
 Integrator output step histogram
 SR is still important
116
MUX-2011
20b 250Hz Sigma-Delta ADC – Topology Choice
 FFSDM  Stability & Recovery Test
 Input overload signal
 The structure recovers from overload
 No reset circuit is need
117
MUX-2011
20b 250Hz Sigma-Delta ADC – Topology Choice
 FFSDM – SC Implementation
118
MUX-2011
20b 250Hz Sigma-Delta ADC – Topology Choice
 FFSDM  Architecture development






Qnoise
DAC non-linearity (Cap mismatch)
Instability / Recovery time
Idle tones
Quantizer VTH Error
FF Adder Gain Error
 Circuit design development
 Opamp performance effects
 Gain, Bandwidth, Slew-Rate
 Sampling Jitter
 Thermal noise
119
MUX-2011
20b 250Hz Sigma-Delta ADC – Topology Choice
 Simulink model
 Transient effects (SR, QN, Jitter, mismatch)
 Small signal effects (Thermal&1/f, Gain&Bandwidth)
120
MUX-2011
20b 250Hz Sigma-Delta ADC – Topology Choice
 FFSDM - Real opamp performance
 Gain = 50dB, UGB = 25MHz, SR = 40V/µs
 Poor opamp gain requirement  LowPowerCons
121
MUX-2011
20b 250Hz Sigma-Delta ADC – Topology Choice
 FFSDM - Real opamp performance
 SNRNoJitter





192.71dB
168.08 dB
192.71 dB
192.71 dB
168.078dB
122
MUX-2011
20b 250Hz Sigma-Delta ADC – Topology Choice
 Dither Avoids Spurious_Tone
generation at low signal-level
 @ Low-Level Multibit ADC behaves
like a single-bit ADC
 Dither is implemented with an
SC branch
 Cdit = 1/10 Cb
 connected at the 2nd-opamp
input
 dith frequency = Fs/4
  input tones at Fs/4, i.e. far
from the signal band
 can be disabled (dithEn signal)
123
MUX-2011
20b 250Hz Sigma-Delta ADC – Implementation
 Input noise reduction
 The aggressive AAF reduces input noise bandwidth
 It reduces settling time of the sampling operation
 The final sampled value depends on charging starting
point
  Sampling error depends on signal amplitude
 THD
124
MUX-2011
20b 250Hz Sigma-Delta ADC – Implementation
 Input noise reduction - Solution
 The sampling capacitor is reset at the beginning of the
sampling phase
  The signal-dependent error is canceled
125
MUX-2011
20b 250Hz Sigma-Delta ADC – Implementation
 1st-opamp design
 1/f Noise  Chopper
 FFSDM
  Reduce swing
 Telescopic cascode
 Different input.vs.output CM
compensated in the SC
structure
126
MUX-2011
20b 250Hz Sigma-Delta ADC – Implementation
 Chopper concept
 Chopper frequency choice: Trade-off motivation
 Low chopping frequency  Larger in-band noise folding
 High chopping frequency  Large-&-frequent opamp output
steps
 Chopper frequency choice  Fs/8
127
MUX-2011
20b 250Hz Sigma-Delta ADC – Implementation
 Chopper concept
 In a two-stage opamp only
the 1st-stage in chopped
 Negligible 2nd-stage 1/f noise
 Smaller 1st-stage output swing
 In a single-stage opamp
  The full opamp is chopped
  Significant output swing
 !!! BUT in FF-SDM
  small 1st-opamp output
swing
  Chopper is not critical
128
MUX-2011
20b 250Hz Sigma-Delta ADC – Implementation
 Chopper
Transient
evolution
 Output1
pink line
 Output2
Green line
129
MUX-2011
20b 250Hz Sigma-Delta ADC – Implementation
 Multibit ADC
 ADC Threshold voltage generation
 Passive SC solution in the comparator
(single-ended version)
 Charge balance
Vc (2) =V in -
Cp
C p + Cm
×VR
 VTH=7  Cp = 7·C & Cm = 1·C
 VTH =5  Cp = 5·C & Cm = 3·C
 VTH =3  Cp = 3·C & Cm = 7·C
Vc (2) =V in -
C p ×VR + + Cm ×VR C p + Cm
=V in -
C p - Cm
C p + Cm
×VR +
130
MUX-2011
20b 250Hz Sigma-Delta ADC – Implementation
 Multibit ADC
 Fully-differential scheme
131
MUX-2011
20b 250Hz Sigma-Delta ADC – Implementation
 Multibit ADC
 Fully-differential scheme
132
MUX-2011
20b 250Hz Sigma-Delta ADC – Implementation
 Multibit DAC
 Fixed total opamp input capacitance
 Independent on the input data
 Fixed total load for VR+ & VR Independent on the input data
133
MUX-2011
20b 250Hz Sigma-Delta ADC – Implementation
 Multibit DAC: 3bit operation example
134
MUX-2011
20b 250Hz Sigma-Delta ADC – Implementation
 Multibit DAC: 3bit operation example
135
MUX-2011
20b 250Hz Sigma-Delta ADC – Simulation
 Ain=-4dBFS, Dither=NO
136
MUX-2011
20b 250Hz Sigma-Delta ADC – Simulation
 Ain=-4dBFS, Dither=YES
137
MUX-2011
Overall System Power Consumption
Current
Consumption
[ μA ]
Supply Voltage
[V]
Power
Consumption
[ mW ]
2200
3.3
7.3
0
3.3
0
Drivers
672
5.0
3.4
Differential MDAC
353
3.3
1.16
ADC
890
3.3
3
Charge Amplifier
Anti-Alias Filter
138