Transcript LDO characterization

LDO characterization
Laura Gonella
Physikalisches Institut Uni Bonn
Status
• Tests performed on the LDO mode of the Shunt-LDO regulator
– Single device characterization
• Line regulation(*)
– T dependence
• Load regulation(*)
– T dependence
• Load transient
– Parallel operation: same Vin, different Vout
• Line regulation
• Load regulation
• Load transient
(*) These
results have already been shown and discussed. They are added here as
useful material for the design review
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Single device characterization
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•
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Both regulators on chip have been tested independently
Results are in good agreement
Shown here results from Reg2
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Line regulation
•
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For a certain Iload, the Vout is
stable as a function of Vin, once
the output is regulated
To have a regulated output up to
Iload = 600mA the Vdrop has to
be at least 200mV
– Even ~270mA for Iload =
600mA and Vout = 1.2V
•
The lower Vout for Iload = 0.6A
is due to the bad load regulation
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Line regulation: T dependence
•
The line regulation is
stable in a T range
from +20°C to -20°C
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Load regulation
•
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For Iload<10mA, the output stage of
the amplifier A1 that controls the
pass transistor is driven out of
saturation which decreases the
regulation loop gain. This explains
the bad load regulation for Iload <
10mA
Investigations are ongoing to
explain the bad load regulation for
Iload > 10mA
– The test setup seems to be fine
– Results on 4 chips from 2 different
wafers agree, excluding process
variation
– Simulations with corners and T are
good
– Ongoing post layout simulations
with extracted parasitics to extimate
the on chip wiring resistance
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Load regulation
Vdrop (V)
Rout (mΩ) @
Vout = 1.2V
Rout (mΩ) @
Vout = 1.5V
0.1
231
155
0.2
164
144
0.3
155
151
0.4
0.5
155
155
153
155
0.6
155
156
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Load regulation: T dependence
•
The load regulation is stable in a T range from +20°C to -20°C
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Load transient
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Vout = 1.2V, Vin = 1.9V
– Need to have Vin high enough to make sure Vdrop is >200mV during the
transient
•
•
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Load current pulse measured
across a 100mΩ resistor
Iload = 66mA → 190mA,
ΔIload = 124mV
Rise time = fall time = 200ns
Pulse width = 10us
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ΔVout = 18.0mV
Rout = 145mΩ
•
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Load transient
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Vout = 1.5V, Vin = 2.0V
– Need to have Vin high enough to make sure Vdrop is >200mV during the
transient
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Load current pulse measured
across a 100mΩ resistor
Iload = 98mA → 330mA,
ΔIload = 232mV
Rise time = fall time = 200ns
Pulse width = 10us
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•
ΔVout = 29.2mV
Rout = 126mΩ
•
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Load transient
•
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This is what happens if Vin is not high enough
Same as previous slide, just with Vin = 1.9V
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Parallel operation
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Reg1 generates Vout = 1.5V
Reg2 generates Vout = 1.2V
The Vin is in common
– The Vdrop on the Vin lines (from supply to the chip pad) is slightly different
so Vin1 ≠ Vin2
– Reg2 sees a Vdrop ≥ 0.4V
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Line regulation
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Iload1 = 380mA
Iload2 = 180mA
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Load regulation
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Iload2 = 180mA, Vout = 1.169V
Iload1 = 0 – 0.6A
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Vdrop (V)
Rout (mΩ)
0.1
173
0.2
145
0.3
153
0.4
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Load regulation
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Iload1 = 380mA, Vout = 1.446V
Iload2 = 0 – 0.6A
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Vdrop (V)
Rout (mΩ)
0.4
153
0.5
155
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Load transient
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Iload1 = 380mV
Iload2 = 58mA → 184mA, ΔIload = 126mV; rise time = fall time =
200ns; pulse width = 10us
Vout2
Vin2
Vout1
Vin1
ΔVout2 = 17.2mV
Rout2 = 137mΩ
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ΔVout1 = 6mV
ΔVin2 = 350mV ΔVin1 = 320mV
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Load transient
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Iload2 = 180mV
Iload1 = 114mA → 348mA, ΔIload = 234mV; rise time = fall time =
200ns; pulse width = 10us
Vout1
Vin1
Vout2
Vin2
ΔVout1 = 30.8mV
Rout1 = 132mΩ
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ΔVout2 = 4.8mV
ΔVin1 = 650mV ΔVin2 = 590mV
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