Transcript Japan business meeting in Milan

RF Synthesizer / PLL
May 2015
© Integrated Device Technology
Wireless Base Stations
Base-band (Digital unit)
Digital Signal Processing
Typically 1 per BTS
DPLL
Digital
Front-End
(DFE)
CPRI Clocks
Ethernet Clocks
DSP
DSP
DSP
DSP
DSP
DSP
Switch
Host
Processor
BTS: Base station
CPRI: Common Public Radio Interface
OBSAI: Open Base Station Architecture Initiative
JESD204B: Serial Interface for Data Converters, JEDEC Std.
ADC
JESD204
Buffer
CPRI
ASIC
Clock
FPGA/
ASIC
SYSREF
CPRI/OBSAI
Network
I/F
Radio (TRx - transceiver)
De-/Modulates the digital signal, owns the air interface
Typically 3 per BTS
RX
RF
RF
Synthesizer
Synthesizer
DAC
TX
ADC
RX
JESD204B
RF Converter
Clock
JESD204B
Buffer
Serial, Diff. Data Lanes
DAC
RF
RF
Synthesizer
Synthesizer
TX
Microwave Point-to-Point
• Key Identified Requirements
& mmW Tx/Rx cards now have a
Tx/Rx stage operating up to 80GHz.
VGA
PA
8V97051
8V97051
LNA
VGA
Baseband
Processing
(FPGA)
Typical Indoor Unit
DAC
LPF
DAC
LPF
DDC
DUC
I/Q
Modulator
VGA
I/Q
Demodulator
LNA
8V97051
ADC
ADC
LPF
ADC
LPF
8V97051
3

Connect to the Antenna
Typical Outdoor Unit
Connect to the Outdoor Unit
Connect to the Indoor Unit
 uW
Wide range of possible frequencies
• Prefer wide tuning range:
–
3 GHz, 5.8 GHz, 6 GHz, 7 GHz, 8 GHz, 10.5 GHz,
11 GHz, 13 GHz, 15 GHz and more
(using external doubler)

Avoids too many IF conversions: LO
supports high frequencies, wide tuning
range

uW Pt-to-Pt use QAM modulation. When
BW increases, the QAM order increases,
and symbols in the constellation become
very close to each others.
• High performance PLL with
integrated VCO
RADAR Systems
Key Trends and Functionalities
 Frequency allocations
• Frequencies potentially close to base
station frequencies
• Performance, Resolution, Accuracy
and Low Spurs
X-band radar system (8 to 12GHz)
Motor
Control
Duplexer
Converter
Clock
ADC
Driver
PA
DDS
MAIN
ASIC
ADC
RF
AMP
RF
AMP
AMP
Buffer
DAC
RF
AMP
LNA
 X-Band radar are used in weather monitoring, air traffic control, maritime vessel
traffic control, defense tracking, and vehicle speed detection for law enforcement
 The first stage mixes the pulsed radar return to a frequency of around 1 GHz
 The second mixes to an IF in the region of 100 to 200 MHz
4
 Enhanced digital signal processing
• Transition to digital as early as possible on
the signal chain
• ADC moving closer to the antenna
• High LO frequencies
Instrumentation
• Key Functionality and Trends
Network Analyzers
 Equipment needs to provide accurate
measurements
− High Resolution
Signal Generators
− Determines the accuracy of the measurements
− 8V97051 supports 16 bits of Frac-N resolution
Spectrum Analyzers
− Very Low Phase Noise
Pre-selector or
Low pass filter
RF Input
− Noise of the equipment will limit its
measurement capability
Cavity
Filter
VGA
Resolution
filters
AMP
RF Input
step
Attenuator
Envelope
Detector and
Video Filter
Sweep function
Often DDS-based
 Extend the measurement capabilities of the
equipment
– Wide Tuning Range
− 8V97051 provides excellent combination of
phase noise performance and tuning range
 Limit power dissipation impacts and address
portable applications
– Power
ADC
Display and Video
processing
− 8V97051 offers ~380 mW Typ
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Distributed Antenna Systems
Low
Res.
RFVGA
Filter
RF
Filt
AAF
High
Gain Dual
IF VGA
Dual
Mixer
AAF
Filter
Low
Res.
RFVGA
RF
Filt
Power
Amp
23 dBm
Duplexers
Tx VCO/
Synth
CIF Mod
RF
Amp
DSA
Dir.
Cplrs
BPFS
Dual IF
VGA
Integration
Power
Amp
23 dBm
Integration
SP2T




Integration
Rx VCO
DSA
Tx VCO/
Synth
CIF Mod
RF
Amp
BPFS
Dual IF
VGA
Analog
Conditioning
and
MultiPlexing
Tx VCO
Loopback
VCO
IF over Ethernet
Block Diagram
Low
Perf.
Mixer
VSWR
Alarm
Addresses the difficult “Indoor Coverage Problem”
Scalable and Flexible. Fiber or Repeater based Backhaul
IF analog signals over Ethernet or RF over Fiber
Power over Ethernet (POE): need low power
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EtherNet
Markets / Applications
Communications
RF cards
Applications
Pt-Pt Microwave
P-MP Microwave
Distributed
Antenna Systems
(DAS)
✓
✓
✓
Military
Industrial and
Instrumentation
✓
✓
✓
✓
Medical
instrumentation
CMTS TRx
✓
✓
Radar
Spectrum analyzers
Signal generators
Network analyzers
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✓
✓
8V97051 RF Synthesizer / PLL
 Best-in-class combination of phase noise, spurious performance, frequency range and power
 Large tuning range to address a wide range of applications in Communications, Industrial, and Instrumentation
 Multiband local oscillator (LO) frequency synthesis in multi-mode base stations
 Eliminates the use of multiple narrow band RF Synthesizers
 Reduces BOM complexity and cost
Product
8V97051
Features
Benefits
• Pin-to-pin and register compatible
with major competing solutions
• Facilitate evaluation at
customers
• -143 dBc/Hz Phase noise @ 1 MHz
offset for a 1.1 GHz output
• Typical phase noise addresses
Blocker specs
• -147 dBc/Hz Phase noise @ 1 MHz
offset for a 700 MHz output
• Allows best possible
performance from the Mixer or
the Modulator / Demodulator
• Power Consumption: 380 mW
(typical) (RF_OUTB disabled)
• Low power consumption:
applications without air flow
• Extended registers for enhanced
features and resolution
• More flexible control of the local
oscillator (LO) function
• Full CMOS process
• Cost effective
8
8V97051 Architecture Overview
9
8V97051 – Value Proposition
Key
Differentiators
• Best combination of phase noise performance and power
• Meets GSM900 receive channel blocker specifications
• Low power dissipation (380 mW)
• Covers multi-standard base station radio cards
• High frequency resolution
Target Apps
•
•
•
•
•
Wireless infrastructure – radio, Tx and Rx paths
Microwave (lower bands)
Radar applications
Instrumentation and medical
Second source for ADI ADF4350/1 and Maxim MAX2870/1
Availability
• In Production
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Theory of Operation
•
N = INT + FRAC/MOD
•
fVCO = fPFD x (INT + FRAC/MOD)
•
With
•
S = 1 if the reference Div2 is used
•
S = 0 if the reference Div2 is not used.
•
Input reference is 10 MHz – 310 MHz
•
By using the input doubler, fPFD is also
S
doubled and the phase noise performance
typically improves by 3dB.
•
While still meeting the following:
 fPFD_MAX = 125 MHz in Frac mode
 fPFD_MAX = 310 MHz in Integer mode
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Theory of Operation
•
8V97051 supports input frequencies
as high as 310 MHz. Implications are:
– PFD frequencies up to 310MHz
– The Band Select logic operates
between 125 kHz and 500 kHz.
The Band Select clock divider
needs to be set to divide down
the PFD frequency to between
125 kHz to 500 kHz (logic
maximum frequency). When
using a high PFD frequency, the
user might need to use the
extended registers to increase
the Band Select clock divider
value.
(*) VCO Band Selection allows the user to select the
right VCO band for the desired output frequency.
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Extended Registers (1/2)
Extra precision
for the LD
EXT_BND_SEL_DIV are Extra 4 MSBs that
extend the Band Select Clock Counter. These
additional bits are necessary for band
selection to divide down to <500 kHz when
high PFD frequencies are used.
Provide 1st, 2nd or
3rd order SDM
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Extended Registers (2/2)
16 bit mode
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RF Output Power
For RF_OUTA and RF_OUTB, the output power can be
programmed from - 4d Bm to + 7 dBm.
15
Output Matching – Resistively Loaded
Assume the input receiver is
self DC biased
 RF_OUT output loaded with a 50 Ω pull up and with an AC coupling capacitor in series
 Amplitude might get attenuated at high frequencies (resistance becomes impedance with some L and
parasitic capacitance – traces, input and output stages, etc.)
 RF_OUT waveform closer to a square signal (in theory), up to a certain frequency
 RF_OUT waveform starts to look more like a sine wave above that frequency
 The resistive load can be use for the whole frequency range of the 8V97051
 Increasing the pull-up resistor value (for example to 100 Ω) while keeping the power settings (constant
current source output stage) increases the RF output power.
 Or just increase the output power settings (recommended)
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Output Matching – Inductively Loaded
Assume the input receiver
is self DC biased
 The 50 Ω pull up resistance can also be replaced by a choke
 Inductive load does not provide a broadband loading scheme. It is only recommended for high
frequencies (i.e >1 GHz), but not recommended for lower frequencies where a high L value would be
needed to keep a reasonable output power (Impedance ZL = 2*π*f*L)
 Inductive loading has two main advantages:
− The output waveform is closer to a sine wave
− The RF output power is optimized
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Fast Lock Mode
••
In fast lock mode, nd
close the switch (FSLW=1)
Let’s
assume a 2 weorder
filter (No R3 or C3)
LBW = (ICP / 2π) (RS * KV) / N
•
Normal
mode: FSLW=0
When FLSW=1
we do two(switch
things: open)
LBW = (ICP / 2π) (RS * KV) / N
1. R
We
increase the charge pump current ICP
value )
S = RS1 + RS2 = 4 * RS1 (damping resistor
Thisuse
increases
loop bandwidth: fc is shifted to a
We
RS2 = the
3*R
S1
higher frequency
fc is the cut frequency
is the
zero frequency
If wefzonly
increase
the charge pump current, then fc will not
be infpais
stable
region.
the pole
frequency
2.
fZ = 1/(2*π*CS*RS)
fP = 1/(2*π*CP*RS)
The user needs to ensure that CS and CP are
wisely chosen so that there is enough margin for
fC (cut frequency) to stay in the stable region.
fZ
fC
fP
fZ
fC
fP
RS becomes smaller
Now RS = RS1 = 1/4 of the previous value in “normal”
mode
It shifts fz and fp to a higher frequency
fc proportional to RS
So fc is shifted back to a lower frequency.
fC
1) and 2) occur simultaneously.
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Stability Region
>3x
>3x
CS
fZ
CP
fC
fP
•
•
•
Case of a 2nd order filter
fZ = 1/(2*π*CS*RS)
fP = 1/(2*π*CP*RS)
•
fC = (ICP / 2π) (RS * KV) / N
•
Rule of thumb: 3* fZ << fC << 3* fP
RS
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Resolution: 16 bit vs. 12 bit
Integer mode:
•
Assuming integer mode, R=1, M0 = 1, and fPFD the PFD frequency, then the output will be:
RF_OUT = fPFD * N, where "N" is the feedback divider value.
•
Channel spacing or output resolution is fPFD
If you change N, then output changes in fPFD steps
•
If there is an output divider “M0", then the output frequency is: RF_OUT = fPFD * N / M0
The output channel spacing is “fPFD/ M0“. The maximum M0 value is 64.
Note that in both cases, the channel spacing in "Hz" is different if M0>1, but the ppm resolution is the
same with or without the output divider.
Fractional mode:
•
•
The output of the PLL with divide by 1 will be: RF_OUT = fPFD * (N + FRAC/MOD)
The minimum channel spacing (by changing FRAC by one step,) is fPFD * (1/MOD) or fPFD/MOD.
•
•
•
With a 12-bit MOD, the minimum channel spacing is fPFD/(212)
With a 16 bit MOD, the minimum channel spacing of fPFD/(216)
That is a 16x improvement over the 12 bit case
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MUX_OUT
Default. Output
disabled.
For Readback
21
Competitive Summary
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Comparison with ADF4350/1: Additional Features and Specs
•
•
•
“Drop-in” replacement: hardware and software compatible
Finer precision for Lock Detect
Several additional features
Features/Performance
8V97051
ADF4350/1
Single supply
Yes
Yes
Fractional resolution
16 (also has a 12 bit mode)
12
Read-back mode
Yes
No
Input frequency range
5 MHz – 310 MHz
10 MHz – 250 MHz
PFD frequencies (Integer mode)
Up to 310 MHz
Up to 90 MHz
PFD frequencies (Frac mode)
Up to 125 MHz
Up to 45 MHz
DSM configuration options to
optimize spur performance
1st, 2nd, 3rd order DSM options
Multiple selectable DSM engine types
3rd order DSM
Serial Interface
Can support I2C or SPI (Bond option)
SPI
Phase Noise
IDT has better phase noise performance
Spurious performance
Power @ 3.3 V (1 Output ON)
IDT has fewer spurs
380 mW
380 mW
23
Comparison with MAX2870/1: Additional Features and Specs
•
•
•
Pin-compatible
Finer precision for Lock Detect
Several additional features
Features/Performance
8V97051
Max2870/1
Single supply
Yes
Yes
Fractional resolution
16 (also has a 12 bit mode)
12
Read-back mode
Yes
No
Input frequency range
5 MHz – 310 MHz
10 MHz – 210 MHz
PFD frequencies (Integer mode)
Up to 310 MHz
Up to 140 MHz
PFD frequencies (Frac mode)
Up to 125 MHz
Up to 125 MHz
DSM configuration options to
optimize spur performance
1st, 2nd, 3rd order DSM options
Multiple selectable DSM engine types
3rd order DSM
Serial Interface
Can support I2C or SPI (Bond option)
SPI
Phase Noise
IDT has better phase noise performance, especially
for lower frequency range (i.e. GSM900)
Spurious performance
Power @ 3.3 V (1 Output ON)
IDT has fewer spurs in fractional mode
380 mW
380 mW
24
Examples of Phase Noise Plots
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8V97051 – 700 MHz RF_OUT (Frac Mode)
FIN
61.44 MHz
FPFD 61.44 MHz
26
8V97051 – 1.1 GHz RF_OUT (Frac Mode)
FIN
61.44 MHz
FPFD 61.44 MHz
27
8V97051 - 1.65 GHz RF_OUT (Frac Mode)
FREF
FPFD
28
61.44 MHz
61.44 MHz
8V97051 – 2.3 GHz RF_OUT (Frac Mode)
FREF
FPFD
29
61.44 MHz
61.44 MHz