Transcript unit 8 - WordPress.com

Subject Name: LINEAR IC’s AND APPLICATIONS
Subject Code:10EC46
Prepared By: Aparna.P
Department: Electronics and Communication
Date:13-5-2015
4/3/2017
UNIT 8
Other linear IC Applications
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555 Timer
Basic Timer circuit
555 timer used as Astable multivibrator
555 timer used as Monostable multivibrator
Schmitt trigger
PLL
D/A and A/D converters
555 Timer
•The 555 timer which gets its name
from the three 5kΩ resistors it uses to
generate the two comparators
reference voltage, is a very cheap,
popular and useful precision timing
device that can act as either a simple
timer to generate single pulses or
long time delays, or as a relaxation
oscillator
producing
stabilized
waveforms of varying duty cycles
from 50 to 100%.
555 Timer
Pin 1. – Ground, The ground pin connects the 555 timer to the negative (0v) supply rail.
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• Pin 2. – Trigger, The negative input to comparator No 1. A negative pulse on this pin “sets” the internal
Flip-flop when the voltage drops below 1/3Vcc causing the output to switch from a “LOW” to a “HIGH”
state.
• Pin 3. – Output, The output pin can drive any TTL circuit and is capable of sourcing or sinking up to
200mA of current at an output voltage equal to approximately Vcc – 1.5V so small speakers, LEDs or
motors can be connected directly to the output.
• Pin 4. – Reset, This pin is used to “reset” the internal Flip-flop controlling the state of the output, pin 3.
This is an active-low input and is generally connected to a logic “1” level when not used to prevent any
unwanted resetting of the output.
• Pin 5. – Control Voltage, This pin controls the timing of the 555 by overriding the 2/3Vcc level of the
voltage divider network. By applying a voltage to this pin the width of the output signal can be varied
independently of the RC timing network. When not used it is connected to ground via a 10nF capacitor to
eliminate any noise.
• Pin 6. – Threshold, The positive input to comparator No 2. This pin is used to reset the Flip-flop when the
voltage applied to it exceeds 2/3Vcc causing the output to switch from “HIGH” to “LOW” state. This pin
connects directly to the RC timing circuit.
• Pin 7. – Discharge, The discharge pin is connected directly to the Collector of an internal NPN transistor
which is used to “discharge” the timing capacitor to ground when the output at pin 3 switches “LOW”.
• Pin 8. – Supply +Vcc, This is the power supply pin and for general purpose TTL 555 timers is between
4.5V and 15V.
Astable Multivibrator
•Assume the o/p of RS Flip-flop is high
then the o/p is high and transistor will be
off. Capacitor will charge through R1 and
R2 to Vcc.
•When this voltage become greater than
2/3Vcc the upper comparator o/p is high
and the o/p of RS f-f is low. The o/p is
low and the transistor will be on the
capacitor will discharge through the R2
and transistor.
•When this voltage becomes less than the
1/3Vcc the lower comparator o/p is high.
•Then the o/p of RS f-f is high circuit o/p
is high and the transistor is off. The
capacitor starts charging through the R1
and R2.This process repeats.
•We will get square wave.
Astable Multivibrator
• The output
waveforms are shown
in fig.
• The capacitor
charges and
discharges between
1/3 Vcc and 2/3 Vcc.
• The output is a
square wave.
Monostable Multivibrator
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When the o/p of RS f-f is high the
circuit o/p is high, the transistor is off
and the capacitor charges through R
to VCC.
When this voltage crosses the
2/3VCC the upper comparator o/p is
high and RS f-f o/p is low and the
circuit o/p is low, the transistor is on
and the capacitor discharges to
ground level.
When the triggering input is applied
at pin 2 and it crosses 1/3 VCC then
the lower comparator o/p is high and
RS f-f o/p is high the ckt o/p is high
and the transistor is off then the
capacitor charges through R to Vcc.
This process will repeat.
Comparison of Multivibrators
Schmitt trigger
• Here two comparators are
internally connected and
externally biased at Vcc/2
through the potential circuit
R1 and R2.
• When the i/p voltage
is(>2/3Vcc – Vcc/2) to
exceed the reference levels
causes the flip flop to
change between set and
reset ,giving the square
wave as output.
PLL
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Phase locked loop is used in radar
synchronization.
It consists of phase detector, LPF,
error amplifier and VCO.
The phase detector is a multiplier
which multiplies the two input signals
and gives the sum and difference
component as o/p.
The low pass filter passes the
difference component and attenuate
the sum frequency component.
The error amplifier produces the dc
voltage signal proportional to the
difference frequency.
This is applied to the VCO (Voltage
Controlled Oscillator) it produces
corresponding changes in the
frequency.
This process repeat until the error is
zero. The PLL is said to be locked.
PLL
• The fig shows the monolithic
PLL or 565 PLL .
• In this all components are
integrated as a single chip.
• It is 14 pin IC.
• The capacitor connected
between pin 7 and 10 and the
resistor 3.6KΩ act as a low
pass filter.
• A short circuit between 4 and 5
connects the VCO o/p to the
phase comparator.
Voltage Controlled Oscillator (VCO)
• The VCO shown in fig which
is 566 IC having 8 pin
configuration.
• The timing capacitor charges
and discharges through a
constant current source.
• The amount of current is
controlled by changing the
voltage Vc applied at the
modulating input.
• The voltages at pin 5 and 6 are
same.
• The voltage across the
capacitor is applied to the
inverting terminal of Schmitt
trigger A2 via A1 buffer.
VCO
• The o/p is designed in between
Vcc and 0.5Vcc.
• If Ra=Rb the voltage at the non
inverting terminal of A2 swings
from 0.5 Vcc to 0.25Vcc.
• When the voltage on the capacitor
Ct exceeds 0.5Vcc the o/p goes
low.
• The capacitor discharges and it
crosses 0.25Vcc ,the o/p goes
High.
• Since the capacitor charging and
discharging times are equal this
gives triangular waveform .
• The Schmitt trigger o/p is applied
to the inverter we will get square
wave.
D/A and A/D Converters
• The block diagram shows the application of A/D and D/A converters used
in digital audio recording and playback.
• The Analog signal is passed through transducer to convert into electrical
signal.
• This is passed through the antialiasing filter and then applied to the sample
and hold circuit then it is applied to the analog to digital converter.
• And then it is passed through the dsp processor and applied to the D/A
converter.
• Then it is passed through the smoothing filter to get proper analog signal.
D/A and A/D Converters
• The schematic of a D/A converter is shown in fig.
• The input is an n- bit binary data and it is combined with the
reference voltage to produce an analog output.
• There are three types of DAC’s
• Weighted resistor DAC
• R-2R Ladder DAC
• R-2R inverted ladder DAC
Weighted Resistor D/A
• The n-bit weighted resistor D/A is shown in fig.
• It is having n no of switches of single pole double throw type.
• If the input is 1 it is connected to reference voltage and if it is zero it is
connected to ground.
• The op-amp can be connected in non inverting mode also.
• It is required wide range of resistors values and the accuracy is depending
on the accuracy of resistor.
• The output current is given by
Weighted Resistor D/A
• The weighted resistor D/A is shown in fig.
• The output of weighted resistor D/A is shown in fig.
• It is a staircase waveform
R-2R Ladder D/A
• The R-2R Ladder D/A is shown
in fig.
• It requires only two resistor
values. The 3 bit DAC is shown
fig corresponding to 100.
• The voltage at node C can be
calculated as
• The output voltage is given by
Inverted R-2R Ladder D/A
• The fig shows the Inverted R2R Ladder D/A.
• The disadvantage of the
weighted resister and R-2R
DAC’s can be eliminated by
this.
• In this the current is not
depending on the input binary
data.
• It is equally divided between
the two resistor branches.
A/D Converter
• The schematic block diagram
is shown in fig.
• The analog input is applied
along with the Start and EOC
control signals it will give the
digital output.
• The start signal tells when to
start conversion and EOC tells
conversion completed after
completing the conversion.
• The digital output is given by
A/D Converter
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The types of ADC’s are
Flash type ADC
Counter type ADC
Successive approximation ADC
Dual Slope ADC
Flash type A/D Converter
• The Flash type A/D Converter is
shown in fig.
• The non inverting terminals of the
comparators are connected to the
analog input.
• The inverting terminals are
connected to the potential divider
network.
• If the analog voltage is greater
than the reference voltage then the
output of the comparator is high
otherwise it is low.
• Then the comparators output are
applied to the encoder.
• Then the output of the encoder is
the digital equivalent of the
analog signal.
Counter type A/D Converter
• The counter type ADC is shown in fig.
• In this the counter output is given to the DAC, the output of DAC is
compared with the analog input if it is less then the output of
comparator is high then the clock pulse is applied to the counter.
• If the DAC o/p is greater than the analog i/p the o/p of comparator is
low no clock pulse is applied to the counter and the counter o/p is
the digital equivalent of analog i/p signal.
• The counter is reset to zero.
• Once again the analog i/p signal is applied the process is repeated.
• The disadvantage of this is it requires more no.of clock pulses.
Counter type A/D Converter
Successive approximation A/D Converter
• The fig shows the block diagram of 8 bit successive approximation
A/D converter.
• In this initially we assume the shift register contents are 10000000.
• It is applied to the DAC and the o/p of DAC is compared with analog
i/p, if it is less than the o/p of comparator is low and the next bit in
the shift register is 1.
• If the DAC o/p is greater than analog i/p, the comparator o/p is high
and the present bit is made 0 and the next bit will be high.
• This process repeats until the 8 clock pulses.
• This is advantage of successive approximation register.
• The register contents gives the digital equivalent of given analog
signal.
Successive approximation A/D Converter
Dual slope A/D Converter
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The dual slope A/D converter is shown in fig.
The circuit consists of buffer, integrator and voltage comparator.
First it integrates the analog i/p for fixed duration of 2n clock periods.
Then it will integrate the reference voltage until the integrator o/p is
zero.
The number of cycles required to get the integrator o/p zero is N
which is proportional to the analog i/p.
From the block diagram initially the switch is connected to Va and
then integrated through integrator.
Then switch is connected to VR and then it is integrated by
integrator until the o/p is equal to zero.
The no.of cycles equal to the digital equivalent of analog signal.
Dual slope A/D Converter