Transcript Active filters

Advanced Analog IC Design
EECT 7326
Prof. Y. Chiu
Fall 2015
Continuous-Time
Active Filters
–1–
Advanced Analog IC Design
EECT 7326
Prof. Y. Chiu
Fall 2015
Introduction
Filtering: most common linear time-invariant (LTI) signal
processing function – selecting the signal bandwidth of interest
(in reality neither linear nor time-invariant)…
Categories: continuous time (CT), discrete time (DT)
analog filter, digital filter
(will focus on CT analog filters for this course)
Frequency domain: low-pass (LP), high-pass (HP), band-pass
(BP)…
Time domain: impulse response, FIR, IIR…
–2–
Advanced Analog IC Design
EECT 7326
Prof. Y. Chiu
Fall 2015
Simple RC Filter
s-plane
R
Vi
C
Vo
sp=-ω0
1
V
1
H(s) = o  s  = sC =
1 1+ sRC
Vi
R+
sC
jω
σ
0
sp = -ω0 = -
1
RC
Continuous-time, 1st-order, one real pole, low-pass
–3–
Advanced Analog IC Design
EECT 7326
Prof. Y. Chiu
Fall 2015
Simple RC Filter
Frequency response
Impulse response
1 - τt
h(t) = e
τ
|H(jω)|
-20dB/dec
-6dB/oct
1
for t ≥ 0,
τ = RC, ω0 =
0
ÐH(jω)
0
ω0
ω0
ω
1
RC
H(t)
1/τ
ω
e-t/τ
-45°
0
-90°
–4–
t
Advanced Analog IC Design
EECT 7326
Prof. Y. Chiu
Fall 2015
General Filter Specs
|H(jω)|
Ideal LPF:
1
• Non-causal
• Infinite complexity
0
ω0
ω
|H(jω)|
αp - passband
ripple (< 1dB)
0dB
Stopband
Passband
αs - stopband
attenuation
More realistic:
• Magnitude response
ωp, ωs, αp, and αs
• Phase response
0
ωp
ωs
ω
Transition
band
–5–
Advanced Analog IC Design
EECT 7326
Prof. Y. Chiu
Fall 2015
Example: 2nd-order VTF
Vo
b
H(s) =  s  = 2
Vi
s + as + b
• Continuous-time
• Where are the poles? (complex conjugate poles for
maximum flatness)
• Low-pass, high-pass, or band-pass?
–6–
Advanced Analog IC Design
EECT 7326
Prof. Y. Chiu
Fall 2015
Passive RLC Filter
R
Vi
L
C
Vo

1
LC
H(s) =
R 1
s2 + s +
L LC
• No active component (low power)
• Inductors are bulky and expensive to realize in IC’s
• Values of R, L, and C will not track each other
–7–
Advanced Analog IC Design
EECT 7326
Prof. Y. Chiu
Fall 2015
Active OP-RC Filter
R2
R4
CA
R1
R
R
CB
R3
Vi
•
It’s active
•
Inductor-less
•
Area efficient
•
Values of R’s and
C’s and their time
co.’s won’t track
each other – may
lead to RC time
constant variations
of as high as 20%
•
RC time constant
enters the VTF in
product form – can
be tuned for
accuracy
Vo
Assuming ideal op amps,

1
R1R 3C A CB
H(s) = 1
1
s2 + s
+
R 4CB R 2R 3C A CB
–8–
Advanced Analog IC Design
EECT 7326
Prof. Y. Chiu
Fall 2015
Continuous-Time Integrator
C2
R1
Vi
Vo
Assuming ideal op amp,
t
1
vo  t  = v in  τ  dτ

R1C2 -∞
Hs =
–9–
Vo
1 1 
s = - 

Vi
s  R1C2 
Advanced Analog IC Design
EECT 7326
Prof. Y. Chiu
Fall 2015
Cascade Filter Design
‒ Biquads
– 10 –
Advanced Analog IC Design
EECT 7326
Prof. Y. Chiu
Fall 2015
Cascade Filter Design
jω
For a real-coefficient H(s):
s-plane
0
H  s  = Hbq1  s   Hbq2  s   Hs  s 
σ
2nd-order
Biquad:
1st-order
K 2 s 2 +K1s +K 0
Hbq  s  = ω 
s 2 +  0  s + ω0 2
Q 
The leading minus sign in Hbq(s) is only for convenience
– 11 –
Advanced Analog IC Design
EECT 7326
Prof. Y. Chiu
Fall 2015
Special Cases of Biquad
K 2 s 2 +K1s +K 0
Hbq  s  = ω 
s 2 +  0  s + ω0 2
Q 
1) If K 2 = K1 = 0 ⇒ LPF
2) If K 0 = K1 = 0 ⇒ HPF
3) If K 0 = K 2 = 0 ⇒ BPF
4) If K1 = 0 ⇒ BSF
– 12 –
Advanced Analog IC Design
EECT 7326
Prof. Y. Chiu
Fall 2015
Q Factor of Poles
sp
jωp
ω0
σp
sp
ω0
Q=
=
2 σp 2 σp
Δ
jω
 ωp 
1
=
1+ 


2
 σp 
σ
0
s-plane
2
ω0 = sp = σ p 2 + ωp 2
– 13 –
Advanced Analog IC Design
EECT 7326
Prof. Y. Chiu
Fall 2015
Signal Flow Graph (SFG) for Biquad
Hbq  s  =
Vo
K s +K1s +K 0
=- 2
Vi
ω 
s 2 +  0  s + ω0 2
Q 
2

ω0
1

V
=
K
+K
s
V
+
V
ω
V


1
2
i
o
0 m
 o
s 
Q



 V = - 1  K0 V + ω V 

i
0 o
 m
s
ω
0




ω0
ω0/Q
Vi
1
K0/ω0
1
-1/s
1
-ω0
1
-1/s
1
1
Vo
1
K1+K2s
Vm
Note: the partition of the biquadratic VTF is not unique
– 14 –
Advanced Analog IC Design
EECT 7326
Prof. Y. Chiu
Fall 2015
OP-RC Implementation
1/ω0
Q/ω0
CA=1
ω0/K0
Vi
CB=1
Vm
-1/ω0
Vo
1/K1
K2
K 2 s 2 +K1s +K 0
Hbq  s  = ω 
s 2 +  0  s + ω0 2
Q 
– 15 –
Advanced Analog IC Design
EECT 7326
Prof. Y. Chiu
Fall 2015
Alternative SFG for Biquad
Recast Hbq(s):
Vo
K 2 s 2 +K1s +K 0
Hbq  s  =
=Vi
ω 
s 2 +  0  s + ω0 2
Q 

1

V
=
K 2sVi - ω0 Vm 
 o
s




 Vm = - 1  K 0 + K1 s  Vi +  ω0 + s  Vo 

s   ω0 ω0 
Q 

ω0+s/Q
Vi
1
K0/ω0+sK1/ω0
1
-1/s
1
-ω0
1
Vm
K2s
– 16 –
1
-1/s
1
1
Vo
Advanced Analog IC Design
EECT 7326
Prof. Y. Chiu
Fall 2015
Alternative OP-R-C Prototype
1/ω0
1/Q
K1/ω0
CA=1
CB=1
Vm
Vi
-1/ω0
Vo
ω0/K0
K2
K 2 s 2 +K1s +K 0
Hbq  s  = ω 
s 2 +  0  s + ω0 2
Q 
– 17 –
Advanced Analog IC Design
EECT 7326
Prof. Y. Chiu
Fall 2015
Cascade Filter Design
jω
For a real-coefficient H(s):
s-plane
0
σ
H  s  = Hbq1  s   Hbq2  s   Hs  s 
2nd-order
1st-order
Section
Biquad 1
(ω01, Q1)
1st-order
Biquad 2
(ω02, Q2)
•
Order of cascade determines the signal dynamic range
•
Optimized using engineering rule of thumb or thru simulation
– 18 –
Advanced Analog IC Design
EECT 7326
Prof. Y. Chiu
Fall 2015
Biquad Cascade Filter Design
• Most flexible arrangement of cascade filter design
• Allow independent, non-interacting control of (ω0, Q) for
pole pairs
• Easy design
• Components need to be scaled for maximum DR and
minimum component spread
• Pass-band sensitivity to capacitance variation is finite
→ Ladder filter can achieve zero sensitivity
– 19 –
Advanced Analog IC Design
EECT 7326
Prof. Y. Chiu
Fall 2015
Scaling of Active Filter
– 20 –
Advanced Analog IC Design
EECT 7326
Prof. Y. Chiu
Fall 2015
Typical Active Multi-Stage Filters
Fi
Vi
S1i
Vout
V1
Ai
V1
Fj
S1j
V1
A2
Sij
…
V2
S2i
…
…
Vin
V2
Vi
Aj
A1
1st-order
Section
Biquad 1
(ω01, Q1)
Biquad 2
(ω02, Q2)
Initial component values may not be optimal...
– 21 –
Vj
Advanced Analog IC Design
EECT 7326
Prof. Y. Chiu
Fall 2015
Freq. Response of Internal Nodes
Vi
|H(jω)|
V1
Vo,max of op amps
Vj
0
ωi ωj
ω
•
Internal signal swings need to be large to max SNR
•
But not too large such that op amps saturate (producing distortion)
– 22 –
Advanced Analog IC Design
EECT 7326
Prof. Y. Chiu
Fall 2015
DR Scaling of ith Integrator (Vi)
Sim
V1
Fi
Sij
Fj
S1i
Vout
V1
Ai
Vi
…
A2
…
V2
S2i
…
…
Vin
V2
Sik
Aj
Vj
A1
•
First find out the peak value of Vi(ω), mostly done with simulation
•
Then find out the ratio ki = Vi,peak/Vo,max
•
Multiply all capacitors connecting at Vi by ki: Fi → Fi*ki, Sij → Sij*ki, …
•
Divide all resistors connecting at Vi by ki: Fi → Fi*ki, Sij → Sij*ki, …
•
Repeat for all internal nodes…
– 23 –
Advanced Analog IC Design
EECT 7326
Prof. Y. Chiu
Fall 2015
After DR Scaling
|H(jω)|
V1
0
Vi Vj
Vo,max of op amps
ωi ωj
ω
Max internal signal swings all line up to Vo,max
– 24 –
Advanced Analog IC Design
EECT 7326
Prof. Y. Chiu
Fall 2015
Scaling for Min. Component Spread
Sim
Fi
Sij
Fj
S1i
Vout
V1
Ai
Vi
…
V1
Xi
A2
…
V2
S2i
…
…
Vin
V2
Sik
Aj
Vj
A1
•
Find out the smallest cap/res connected to Xi – the summing node of Ai
•
determine the optimum scaling factor mi to minimize spread
•
Multiply all capacitors connected to Xi by mi: Fi → Fi*mi, Sji → Sji*mi, …
•
Divide all resistors connected to Xi by mi: Fi → Fi*mi, Sji → Sji*mi, …
•
Repeat for all integrators…
– 25 –
Advanced Analog IC Design
EECT 7326
Prof. Y. Chiu
Fall 2015
Scaling of Active Filter
• DR and min spread scaling do not take op-amp loading into
account – lots of work if individual op amps are sized to meet
the settling time constraint
• Upon the completion of scaling, simulation needs to be
performed on the resulting filter to find out the overall SNR
• If SNR is lower than the spec, capacitors and op amps need to
be scaled up and resistors scaled down to meet the SNR spec
(think about how integrated output noise behaves)
– 26 –
Advanced Analog IC Design
EECT 7326
Prof. Y. Chiu
Fall 2015
Ladder Filter Design
– 27 –
Advanced Analog IC Design
EECT 7326
Prof. Y. Chiu
Fall 2015
Motivation
• Cascade filter design
– Sensitive to component variations, especially high-Q poles
• Ladder filter design
– Achieves zero sensitivity to component variations
– Discrete CT LC filters with very high-Q poles are built with ladder
structures over the years
– 28 –
Advanced Analog IC Design
EECT 7326
Prof. Y. Chiu
Fall 2015
Ladder Filter
RS
Vin
L2
V1
L4
V3
I2
I4
C1
C3
V5
C5
RL
Vout
Reactance two-port
•
Doubly terminated reactance two-port network
•
Delivers the optimum power matching in the passband
•
∂|Vout|/∂Zi = 0 for all L’s and C’s → low sensitivity
– 29 –
Advanced Analog IC Design
EECT 7326
Prof. Y. Chiu
Fall 2015
State Space of Ladder Filter
RS
L2
V1
V3
I2
Vin
Pick –V1, -I2, V3 as
the state variables
for synthesis
C1









C3
RL
Vout
-V1 = -
1  Vin - V1 
-I2 

sC1  R S

(1)
-I2 = -
1
 V1 - V3 
sL 2
(2)
V3 = -

1  V3
-I

2
sC3  RL

(3)
– 30 –
Advanced Analog IC Design
EECT 7326
Prof. Y. Chiu
Fall 2015
Signal Flow Graph (SFG)
Vin
1/RS
1/RS
1
-1
sC1
-I2
1
-1
sL2
-1
-1
sC3
-1
-V1









V3
-V1 = -
1  Vin - V1 
-I2 

sC1  R S

(1)
-I2 = -
1
 V1 - V3 
sL 2
(2)
V3 = -

1  V3
-I

2
sC3  RL

(3)
– 31 –
1/RL
Advanced Analog IC Design
EECT 7326
Prof. Y. Chiu
Fall 2015
CT OP-RC Ladder Filter
RS
Vin
RS
1
C1
-I2
1
L2
C3
-1
-1
-V1
V3
•
Three free state variables → three op amps
•
A.k.a the leapfrog ladder structure
– 32 –
RL
Advanced Analog IC Design
EECT 7326
Prof. Y. Chiu
Fall 2015
Transmission Zeros
Elliptic LPF
10
C2
0
RS V1
L2
-10
V3
-20
I2
C1
C3
RL
Vout
dB
-30
Vin
-40
-50
-60
-70
1
ωz =
L 2C2
-80
10
6
10
Freq
– 33 –
7
Advanced Analog IC Design
EECT 7326
Prof. Y. Chiu
Fall 2015
Transmission Zeros
IC2
C2
IC2  into node 1 = sC2  V3 - V1  = sC2 V3 + sC 2  -V1 

IC2  into node 3  = sC2  V1 - V3  = sC 2 V1 + sC 2  -V3 
IC2'
V1
V3
sC2·V3
sC2·V1
RS
L2
V1
V3
I2
Vin
C2
C1
– 34 –
C3
C2
RL
Vout
Advanced Analog IC Design
EECT 7326
Prof. Y. Chiu
Fall 2015
Modified SFG with Derivatives
sC2
sC2
Vin
1/RS
1/RS
1
-1
s(C1+C2)
-I2
1
-1
sL2
-1
-1
s(C2+C3)
-1
-V1
V3
– 35 –
1/RL
Advanced Analog IC Design
EECT 7326
Prof. Y. Chiu
Fall 2015
OP-RC Ladder Filter w/ Derivatives
C2
C2
RS
Vin
RS
1
C1+C2
-I2
L2
C2+C3
-1
-1
-V1
•
1
V3
Derivative input paths implemented with capacitors
– 36 –
RL
Advanced Analog IC Design
EECT 7326
Prof. Y. Chiu
Fall 2015
Other Active Filters
– 37 –
Advanced Analog IC Design
EECT 7326
Prof. Y. Chiu
Fall 2015
Tow-Thomas Biquad
R3
R1
C1
R4
R8
R7
Vout
R2
Vin
R6
C2
• Low sensitivity
• Non-interactive
tuning property
R5
[1] P. E. Fleischer and J. Tow, "Design formulas for biquad active filters using three
operational amplifiers,“ Proceedings of the IEEE, vol. 61, pp. 662-3, issue 5, 1973.
– 38 –
Advanced Analog IC Design
EECT 7326
Prof. Y. Chiu
Fall 2015
Design Equations for Tow-Thomas
ms 2 + cs + d
Hs = 2
s + as + b

R8 2
R8
1  R 8 R1R 8 
s +

s +
R
R1C1  R 6 R 4R 7 
R 3R 5R 7C1C 2
Vout
s = - 6
R8
1
1
Vin
s2 +
s+
R1C1
R 2R 3C1C2 R 7
R1 =
k1
1
1
, R2 =
, R3 =
aC1
k1k 2
bC2
R5 =
k1 b
1
, R 6 = R 8 , R 7 = k 2R 8 .
dC2
m
1
1
1
, R4 =
,
k 2  ma - c  C1
bC1
Note: C1, C2, k1, k2, R8 are free parameters
– 39 –
Advanced Analog IC Design
EECT 7326
Prof. Y. Chiu
Fall 2015
Sallen-Key LPF
C1
R1
B
R2
Vin
K
A
Vout
C2
•
OP-RC active filters are ideally insensitive to bottom-plate stray caps
•
Sallen-Key is sensitive to bottom-plate parasitics at node A and B
– 40 –
Advanced Analog IC Design
EECT 7326
Prof. Y. Chiu
Fall 2015
Design Equations for SK LPF
C1
R1
B
R2
Vin
Vout
K
A
C2
G  ω0 2
Hs =
 ω0 
2
2
s +
s
+
ω
0

Q


ω0 =

Q=
ω0
,
1
1
1- K
+
+
R1C1 R 2C1 R 2C2
G = K.
– 41 –
1
,
R1C1  R 2C2
Advanced Analog IC Design
EECT 7326
Prof. Y. Chiu
Fall 2015
Sallen-Key BPF
R2
R1
A C2
B
Vin
K
C1
Vout
R3
Still sensitive to parasitic capacitance at node A and B
– 42 –
Advanced Analog IC Design
EECT 7326
Prof. Y. Chiu
Fall 2015
Design Equations for SK BPF
R2
R1
A C2
B
Vin
K
C1
Vout
R3
ω0 =
ω 
G 0 s
Q 
Hs =
 ω0 
2
2
s +
s
+
ω
0

Q 
Q=

G=
– 43 –
R1 +R 2
,
R 3  R1C1  R 2C2
ω0
,
K
R1C1
.
1
1
1
1- K
+
+
+
R1C1 R 3C1 R 3C 2 R 2C1
1
1
1
1- K
+
+
+
R1C1 R 3C1 R 3C 2 R 2C1
Advanced Analog IC Design
EECT 7326
Prof. Y. Chiu
Fall 2015
MOSFET-C Active Filter
– 44 –
Advanced Analog IC Design
EECT 7326
Prof. Y. Chiu
Fall 2015
MOSFET Resistor
VGS
S
G
IDS
VDS=VGS-Vth
D
VGS
S
D
0
VDS
•
MOSFET in triode region is a variable resistor
•
Compact, low parasitics compared to large-value resistors
– 45 –
Advanced Analog IC Design
EECT 7326
Prof. Y. Chiu
Fall 2015
MOSFET Resistor
In triode region, IDS = μCox
Small signal,
W
1
2
V
V
V
V


GS
th
DS
DS 
L 
2

∂I
1
W
= DS = μCox  VGS - Vth - VDS 
RDS ∂VDS
L
= μCox
W
 VGS - Vth  for VDS = 0
L
But the large-signal response is quite nonlinear
– 46 –
Advanced Analog IC Design
EECT 7326
Prof. Y. Chiu
Fall 2015
A Linear (Diff.) MOSFET Resistor
VG
V1 = Vic +
V1
V2
In triode region, IDS = μCox
Vi
V
, V2 = Vic - i
2
2
W
1
2
V
V
V
V


GS
th
DS
DS

L 
2
= μCox
W
1
2
V
V
V
V
V
V
V





G
th
2
1
2
1
2

L 
2
= μCox
Vi 
W 
1 2
V
V
V
+
V
Vi 
 G th ic
 i

L 
2
2 
= μCox
W
 VG - Vth - Vic   Vi
L
MOSFET resistor is linear when driven by balanced differential signals!
– 47 –
Advanced Analog IC Design
EECT 7326
Prof. Y. Chiu
Fall 2015
Rudell VGA + Mixer
• M9-M15 comprise
the CMFB circuit
• Gain adjustment
by varying IGain
[2] J. C. Rudell et al., “A 1.9-GHz wide-band IF double conversion CMOS receiver for
cordless telephone applications,” IEEE Journal of Solid-State Circuits, vol. 32, pp.
2071-88, issue 12, 1997.
– 48 –
Advanced Analog IC Design
EECT 7326
Prof. Y. Chiu
Fall 2015
MOSFET-C Integrator
VC
C
C
M1
Vi+
ViM2
C
Vo+
Vo-
=
Vi+
Vi-
C
Vo+
Vo-
•
Sources of M1 and M2 are ideally always equal-potential
•
Fully differential circuit rejects the 2nd-order harmonic (and all even-order
distortions)
•
Triode resistance significantly depends on process (threshold, mobility,
etc.), temperature, and VDD → Filter response needs tuning
– 49 –
Advanced Analog IC Design
EECT 7326
Prof. Y. Chiu
Fall 2015
Frequency Tuning
– 50 –
Advanced Analog IC Design
EECT 7326
Prof. Y. Chiu
Fall 2015
Master-Slave Tuning
VC
Tuning circuit
(master)
M1
C
f/b
control
• Master sets M1-C time
constant to an off-chip
reference thru f/b
VC
VC
…
•
C'
M1'
…
• M1-M1' and C-C' are
matched devices
Active filter
(slave)
• Slave integrator time
constant follows that of
the master
Subject to device mismatch between the master and slave
– 51 –
Advanced Analog IC Design
EECT 7326
Prof. Y. Chiu
Fall 2015
Req Matching
i1
i
C
+V
i2
R
R
-V
VC
Rr
C
+V
Ф1
Cr
Ф2
VC
Ф2
Ф1
C
+V
R
-Rr
ΔQ = VCr =
VC
V
T ⇒ RCr = T
R
[3] R. Geiger, P. Allen, and N. Dinh, “Switched-resistor filters - A continuous time
approach to monolithic MOS filter design,” IEEE Transactions on Circuits and
Systems, vol. 29, pp. 306-315, issue 5, 1982.
– 52 –
Advanced Analog IC Design
EECT 7326
Prof. Y. Chiu
Fall 2015
Req Matching
R
VC(t)
C
+V
Ф1
Cr
Ф2
VC
Ф1
0
Ф2
Ф1
Ф2
Ф2
Ф1
t
ΔQ = VCr =
V
T
R
⇒ RCr = T
•
Charge from R is continuous but discrete from Cr
•
VC(t) should be sampled at the end of Ф2 and held before being applied to
the MOSFET gate
•
LPF can be used instead of ZOH, but error will be introduced
– 53 –
Advanced Analog IC Design
EECT 7326
Prof. Y. Chiu
Fall 2015
Phase Locking
Phase
shift
fref
V1
V2
PD
Vp
VC
C
R
[4] K. R. Rao, et al., “A novel ‘follow the master’ filter,” Proceedings of the IEEE, vol. 65,
pp. 1725-6, issue 12, 1977.
[5] R. Geiger, P. Allen, and N. Dinh, “Switched-resistor filters - A continuous time
approach to monolithic MOS filter design,” IEEE Transactions on Circuits and
Systems, vol. 29, pp. 306-315, issue 5, 1982.
– 54 –
Advanced Analog IC Design
EECT 7326
Prof. Y. Chiu
Fall 2015
Phase Locking
V1,V2
PD
V1
t
Δφ
Vo1
Vo1,Vo2
Vp
t
V2
Vo2
Vp
<Vp>
t
•
Phase detector converts the phase difference b/t V1 and V2 into a pulse with
bipolar average <Vp>
•
The trailing integrator keeps integrating when <Vp> ≠ 0 holds
– 55 –
Advanced Analog IC Design
EECT 7326
Prof. Y. Chiu
Fall 2015
Phase Locking
<Vp>
Phase
180o
-90o
90o
270o
0o
-45
Δφ
90o
45o
0o
-45o
fref
V2
PD
ÐV1
Δφ=135o
Δφ=45o
Δφ=90o
V2
jωRC
=
Vref 1+ jωRC
V1
o
ÐV2
Vp
VC
Δφ = 90º ⇒ RC =
C
R
1
ωref
•
<Vp> = 0 holds for Δφ = 90º, -90º, … In steady state, V2 leads V1 by 90º
•
Negative f/b sets the pole freq. of the HPF formed by C & R to ωref
– 56 –
ω
Advanced Analog IC Design
EECT 7326
Prof. Y. Chiu
Fall 2015
CT Ladder Filter Tuning
RS
Vin
L2
L4
C1
C3
C5
RL
Vout
Vout
∫
∫
∫
∫
∫
Vin
• 5th-order Chebyshev-I all-pole continuous-time filter
• Integrators are realized by Gm-C active structures
– 57 –
Advanced Analog IC Design
EECT 7326
Prof. Y. Chiu
Fall 2015
Gm-C Active Integrator
VC
IC
Gm =
C
Vi
i
Vo
•
I
i
= C
Vi 2VT
Vo
G 1
=- m 
Vi
C s
Differential input with programmable gain constant Gm/C
– 58 –
Advanced Analog IC Design
EECT 7326
Prof. Y. Chiu
Fall 2015
Frequency Locking
VCO
-1
∫
VC
Vin
∫
∫
…
ωosc = ω1ω2
Vout
∫
PD
R2
VC
∫
fref
R1
…
Active filter (slave)
[6] K.-S. Tan and P. R. Gray, "Fully integrated analog filters using bipolar-JFET
technology," IEEE Journal of Solid-State Circuits, vol. SC13, pp. 814-821, issue 6,
1978.
– 59 –
Advanced Analog IC Design
EECT 7326
Prof. Y. Chiu
Fall 2015
VCO
R1
R2
-1
V0
V1
V2
ω1
 ω1 R 2 - R1
 1+ s R +R
1
2


ω2

s

-
ω2


ω1
ω1  R 2 - R1
V1 - V2 
 V1 = -  V0 - V2  = - 

s
s  R1 +R 2


ω2

V
=
V1
 2
s
ω1 
s   V1 
R -R
   = 0 ⇒ Δ = s 2 + 2 1 ω1s + ω1ω2 = 0
R1 +R 2
  V2 
1 

2
s = ω1ω2
s1 + s 2 =
⇒ ωosc = ω1ω2 ,
R1 - R 2
ω1 ≥ 0 ⇒ R1 ≥ R 2
R1 +R 2
– 60 –