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LPRDS – CMS – 2011
Per Cell Management Design
Presentation Outline
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Introduction
Project Goals
One Board Per Pack
ESS Controller Board
System Communication
Mechanical Design
ATP / Requirements Analysis
Budget
Schedule
Presentation Outline
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Introduction
Project Goals
One Board Per Pack
ESS Controller Board
System Communication
Mechanical Design
ATP / Requirements Analysis
Budget
Schedule
3-year Senior Design Project
2009 Legacy Work
2010 Legacy Work
2011 Projected Work
Lafayette Photovoltaic Research and
Development System (LPRDS)
LCD Display
SCADA Interface Box (SIB)
Fit PC
System Status Display
Filter Inverter Box (FIB)
Switch Controller / Energy Management Unit
(SC / EMU)
Energy Storage System (ESS)
Transformer
LPRDS-CMS-2011
• Finish a per-cell balancing
scheme for the 64-cell
LiFePO4 battery pack.
• Complete design so that
energy storage system is
capable of being utilized
by the LPRDS system.
Plan of Work
• Develop a “Slave Board” (OBPP PCB) which will
balance during charge/discharge a pack of 4
cells
• Develop a “Master Board” (ESSCB PCB) which
will control the functioning of the OBPPs to
charge/discharge/bypass a particular cell.
• Develop a “Stand-alone” mode for the OBPP in
which a pack and OBPP together do not need the
master to make decisions for bypassing during
charge/discharge.
Aggregate Battery
Stack with OBPP
PCBs
Energy Storage
System Master
Controller Board
(ESSCB PCB)
Presentation Outline
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Introduction
Project Goals
One Board Per Pack
ESS Controller Board
System Communication
Mechanical Design
ATP / Requirements Analysis
Budget
Schedule
Project Goals
• Develop a One Board Per Pack PCB which can
handle the balancing of a 4-cell battery pack.
• Modify previous ESS Controller Board which can
control individual OBPP packs for total pack
charging/discharging.
• Develop method of visually demonstrating
operation of ESS.
Presentation Outline
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Introduction
Project Goals
One Board Per Pack
ESS Controller Board
System Communication
Mechanical Design
ATP / Requirements Analysis
Budget
Schedule
One Board Per Pack (OBPP)
One Board Per Pack :: Key Features
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Individual cell balancing capabilities
Two Modes of Operation (Slave & Stand-alone)
Boots in Stand-alone Mode
LEDs indicating operational state of pack
LEDs indicating operation of bypass
Scalability
Temperature Fail-Safe System
One Board Per Pack :: Design
One Board Per Pack :: Design
• Resistive burn-off bypass solution
• Independent redundant temperature safety
system (RTSS)
• Individually addressable packs for master-slave
configuration
• Stand-alone operation with charge state
controlled open collector output
• Implements I2C communication in master-slave
configuration
• *Current sensing capability
Cell Balancing Design
• Breakdown of design trade-offs
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Active vs. Passive Balancing
Level of Integration
Delegation between Controller and OBPP boards
Scalability
Layout Space
Cost
Manufacturability
Availability
Active Vs. Passive Balancing
• Active: Using capacitive or inductive loads to
shuttle charge from higher charged cells to lower
charged cells.
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Is more efficient from a power perspective
Has scalability issues
OBPP boards are larger and handle more work
Manufacturability issues
Active Vs. Passive Balancing
• Passive: Bypasses cells and burns off the excess
charge from the cell.
▫ Better large-stack scaling
▫ Burn off can be significant
▫ Controller board handles decision-making
Bypass Design
• Grounding the floating reference
• Choosing a resistor value
• Choosing a suitable transistor
Bypass Design – Resistor Choice
Bypass Design
Bypass Design – Transistor Simulation
These numbers give a maximum power dissipation of
2.122 * 1.5 = 6.74W, which is about 35 degree temp rise
using the thermal resistance of the resistor alone.
Bypass – Final Thoughts
• Only the most recent simulations
• Several different iterations of components and
control schemes
• Final design can reasonably bypass 1/5 C at full
charge
• Limitations of the bypass circuit heavily
influenced the balancing algorithm
Critical Monitoring
• Battery Voltages
• Temperature
▫ On board and RTSS
• Current
▫ Direction and Amplitude
• Open-Drain Output
▫ Optional Automatic Control
• Fuse
Critical Monitoring - Voltage
Critical Monitoring - Voltage
• Difference Amp to buffer and isolate battery
voltages
• Monitors for voltage thresholds that indicate a
full or empty state
• Balancing algorithm requires them
Critical Monitoring - Temperature
• RTSS discussed later
• Voltage output temperature sensors for noncritical temperature monitoring
Critical Monitoring - Current
• A relatively new addition
• Gives a way to independently judge whether the
pack is charging or discharging
• Required for the balancing algorithm
Critical Monitoring – Output Pin
• Based entirely on OBPP calculations
• Allows the user to have a charging circuit that is
autonomous
• An open drain output from the microcontroller
Critical Monitoring - Fuse
• Another new addition
• Will protect the CMS from currents above 25A
Digital I/O
• Master/OBPP communications will be over I2C
▫ OBPP will have a 4 bit switch addressing
• OBPP will transfer from Standalone to Slave
when I2C becomes active
• Master commands override OBPP automated
tasks
Redundant Temperature Safety System (RTSS)
• Independent functionality to shut down system
when temperature exceeds 65°C
• Connection to each OBPP using AD22105 “Low
Voltage, Resistor Programmable Thermostatic
Switch” Integrated Circuit
▫ (Setpoint accuracy = 2°C)
• When any board exceeds the temperature limit, the
switch within the safety loop is activated and the
system shuts down.
Overall RTSS
• Does not work as
stand-alone pack
• Must be connected to
ESSCB Safety Loop
RTSS parts on OBPP
To other OBPPs
OBPP Connection to Safety Loop
to OBPPs
OBPP Thermal Analysis (Charging/Discharging)
Copper
FR4 (Circuit board)
Aluminum
Lithium Iron Phosphate
(Aluminum)
Acrylic Plastic
OBPP Thermal Analysis (Bypass Scenario)
Copper
FR4 (Circuit board)
Aluminum
Lithium Iron Phosphate
(Aluminum)
Acrylic Plastic
Stationary Analysis (1 cell heating)
Stationary Analysis (4 cells heating)
Stationary Analysis (Conductive slabs)
Stationary Analysis (Bypass scenario)
Time Dependent (1 cell)
Time dependent (Bypass Scenario)
OBPP Operational Verification
• Bypass LEDs to indicate resistive bypassing
• LEDs to indicate charge/discharge and mode of
operation
Solid – Charged
Blink – Charging
Solid – Discharged
Solid – Slave
Blink – Discharging Blink – Stand-alone
Solid – Bypassing
OBPP Additional Notes
• Multiple levels of electrical isolation
▫ Microcontroller/bypass loop
▫ I2C on OBPP and Master board
▫ RTSS isolated as well
OBPP Firmware
• Stand-alone Mode
• Slave Mode
• Cell Balancing Algorithm
OBPP Firmware - Standalone
• Begins after a reset or losing the I2C clock signal
• Watches for voltage thresholds
• Cell balancing is enabled
• Waits for I2C connection
• First firmware development milestone
OBPP Firmware – Slave
• Many of the same responsibilities
• If no explicit instructions from the master, very
similar to Standalone
• Master commands are executed first and
prioritized
OBPP Firmware
Standalone Mode
Slave Mode
Check
Status
Check
Status
Discharging
Charging
Sleep
Bypass
Discharging
Charging
Sleep
Bypass
Bypass
Bypass
Cell Specifications
• Type- Lithium Iron Phosphate (LiFePO4)
• Nominal Voltage - 3.2 V
• Capacity – 10 A-h
Cell Behavioral Simulation
Cell Behavioral Simulation
Cell Behavioral Simulation
Average Slope (V/min)
0.00208
Cell Balancing Algorithm (1 Cell)
• Charging
▫ If the voltage of any cell in a pack of 4 is greater than any of
the other 3 cells by more than 40mV, then that cell will go
into bypass for 20 minutes.
▫ During charge, a green LED on the OBPP will blink
▫ If the voltage of any cell exceeds 3.8V, then the pack will be
considered fully charged, and the CMS will notify the user
to discontinue charging (this must happen regardless of
whether the cell is in bypass or not)
▫ If the temperature of any cell exceeds 40° above ambient,
then the CMS will notify the user to discontinue charging
(this must happen regardless of whether the cell is in
bypass or not)
Cell Balancing Algorithm (1 Cell)
• Discharging
▫ If the voltage of any cell in a pack of 4 is less than any of the
other 3 cells by more than 40mV, then all other cells will go
into bypass for 20 minutes.
▫ During discharge, a Red LED on the OBPP will blink
▫ If the voltage of any cell drops below 2.8V, then the pack
will be considered fully discharged, and the CMS will notify
the user to discontinue discharging (this must happen
regardless of whether the cell is in bypass or not)
▫ If the temperature of any cell exceeds 40° above ambient,
then the CMS will notify the user to discontinue discharging
(this must happen regardless of whether the cell is in
bypass or not)
Cell Balancing Algorithm (1 Cell)
• OFF
▫ If the CMS is in the OFF state, either a Solid Red
LED will indicate that the pack is fully discharged,
or a Solid Green LED will indicate that the pack is
fully charged
▫ If the CMS is in the OFF state, no cells will be in
bypass
▫ If the CMS is in the OFF state, all time
differentials will be set to zero
Cell Balancing Algorithm (1 Cell)
• Bypass
▫ If a cell is in bypass, a Solid Red LED in parallel
with the Bypass resistor will be lit
Cell Balancing Algorithm (1 Cell)
LPRDS-CMS-2011
Cell Balancing
Algorithm
State Diagram
Justin Bunnell
3/9/2011
Reset ||
Change in Status
V > (40mV + V of any
Cell) || V > 3.5V
Bypass Cell
Bypass LED
Blink Green LED
Time < 20 min
isCharging
Charging
Blink Green LED
Check Status
ELSE
Temp > 60°C
|| V > 3.8V
Temp > 60°C ||
V > 3.8V
OFF
Solid Red/Green
Always
Temp > 60°C || V <
2.8V
isDischarging
Discharging
Blink Red LED
Temp > 60°C Any Other Cell is in
|| V < 2.8V
OFF State
ELSE
V < (V of any Cell –
40mV)
Bypass Cells
Not in This State
Blink Green LED
Time < 20 min
Cell Balancing Simulations
Cell Balancing Simulations
Cell Balancing Simulations
Cell Balancing Simulations
Cell Balancing Simulations
Cell Balancing Simulations
Cell Balancing Simulations
Cell Balancing Simulations
Power Dissipation (W)
Power dissipation across power resistor
Time
Cell Balancing Algorithm Pros
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Cell Balancing within 10 charge/discharge cycles
Ability to be done in Standalone Mode
Relative Simplicity
Strict conditions to keep cell within safe ranges
Bypass current does not scale at same rate as
charge current
Cell Balancing Algorithm Cons
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Cell Characteristic Differences
State of Health of Cell
High State Of Charge Mismatch
Power Losses to Bypass Resistor (especially
during discharge cycle)
• Losing balancing time by limiting maximum
temperature (limit to bypass resistance)
• Minimum charge and discharge currents
Presentation Outline
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Introduction
Project Goals
One Board Per Pack
ESS Controller Board
System Communication
Mechanical Design
ATP / Requirements Analysis
Budget
Schedule
ESS Controller Board
ESS Controller Board … redesigned
HV Lines
I2C
NC
RS-485
PIC 18F4525
12/5 V
Supplies
Temp Safety
Loop
To ABS
(Aggregate
Battery
Stack)
NC
NC
Safety
ESS Controller Board :: Key Features
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Fuel Gauge Algorithm (FGA)
I2C Interface Communication with OBPP
I2C Interface LCD Screen
4 LEDs indicating state of CMS
Current Sensing
RS-485 Communication with SCADA
Redundant Temperature Safety System (RTSS)
ESS Control Board
PRELIMINARY DESIGN
ESS Control Board
• Primary Functions:
▫ Transmit CMS information (Voltage,
Temperature, Current) to SCADA system
▫ Monitor current
 Fuel Gauge Algorithm
▫ High Voltage Indicator
▫ CMS Display (LED’s and/or LCD)
▫ Safety Loop
▫ Override OBPP’s if necessary
ESSCB Continued…
• Re-use PIC18F4525
• Re-use code from last year
• Re-use power sources, sensors, terminals, LED’s,
etc from last year
• Re-use safety loop
• Communication
• RS-485 Interface with SCADA system (SPI)
• I2C Interface with OBPP’s and LCD
• For the PIC I2C and SPI share the same line
 TI I2C I/O Expander
ESSCB Continued…
• Fuel Gauge Algorithm
• Coulomb counting
 Use current sensor to measure charge in and out of
cells
 Reset to full capacity at full voltage threshold
ESSCB Continued…
• Display
• Several LED’s: Charging, Discharging, Fault, 30V
Indicator
• LCD Display
 I2C interface
 System Reset
 System Power
ESS Bill of Materials
Part number
Description
Price
Quantity
Subtotal
CFA533-YYH-KC
LCD Panel/ Keypad
$54.84
1
$54.84
LCD Cable
$5.00
1
$5.00
PIC18F4525
Microntroller
$5.60
1
$5.60
ADUM2250
Opto
$6.00
3
$18.00
LM2901
Comparator
$1.20
1
$1.20
LED-Green
$0.62
6
$3.72
HXS 20-NP
Current Sensor
$14.00
1
$14.00
M57184N-715B
Voltage Regulator
$7.81
1
$7.81
LM2936
Voltage Regulator
$1.93
1
$1.93
555-1058-ND
Voltage Regulator
$12.10
1
$12.10
PCB
$66.00
1
$66.00
6N135
Optoisolator
$0.73
1
$0.73
SN75240P
EDS Protection
$1.15
1
$1.15
BS170
Mosfet
$0.23
1
$0.23
tca9554a
I/O Expander
$2.84
1`
$2.84
$15.00
1
$15.00
TOTAL:
$210.15
HLMP-1790-A0002
Caps, Resistors, Connectors
SCADA Communication
LPRDS Software Architecture 2010
SCADA Communication
• Add additional parameters for query
• Increase polling times/ polling delay
• Poll ESS  ESS Poll OBPP  OBPP Respond 
ESS Respond to OBPP
System Communication
1
2
3
4
5
6
7
8
RS-485 SCADA
Communication
(half-duplex &
daisy-chained)
RPI
EMU
16
15
14
13
12
11
10
9
ESS
I2C
Communication
(half-duplex)
SIB
FitPC
Presentation Outline
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Introduction
Project Goals
One Board Per Pack
ESS Controller Board
System Communication
Mechanical Design
ATP / Requirements Analysis
Budget
Schedule
Mechanical Design
Pack Indicators & Heatsink Possibilities
CELL 1 BYPASS
CELL 2 BYPASS
CHARGE
DISCHARGE
MODE
Heatsink
CELL 3 BYPASS
CELL 4 BYPASS
Negative
Terminal
Female
Plug
Male Wire
Connector
Female
Wire
Connector
2-Position
Terminal
Block
Nylon
Standoff
Positive
Terminal
Wire harness 1
(packs 1-8)
Wire harness 2
(packs 9-16)
Physical Dimensions
8 mm
53 mm
21 mm
15 mm
160 mm
107 mm
117 mm
Energy Storage
Manual Battery Disconnect
Status of ESS
DANGER
Presentation Outline
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Introduction
Project Goals
One Board Per Pack
ESS Controller Board
System Communication
Mechanical Design
ATP / Requirements Analysis
Budget
Schedule
Acceptance Test Plan (ATP)
• Modified the requirements of the system
▫ Agreed upon by Professor Nadovich
• Testing at the highest level: full CMS
• All requirements not verified at top level:
▫ Low-level Testing (QA Audit)
▫ Analysis (Technical Memos)
• Requirements are checked off on the Acceptance
Test Report (ATR) as they are met
• ATR is based on the ATP
Expected Tests
• ATP Test 001
• Demonstrates per cell battery management
• Charge every cell to maximum capacity
• Stand alone operation
• Operate for at least 24 hours autonomously
• QA Test 001
• Prevent over-charge or over-discharge
• QA Test 002
• Verifies operation of SCADA system
• QA Test 003
• 30V Indicator LED
Enhanced Requirement Analysis
• Breakdown of the ATP
• Matches each of the requirements with its
respective top-level or low-level test
ATP T001
R002-2
X
R002-3
X
R002-4
R002-5
QA Audit R002-4
QA Audit R002-6
X
X
R002-6
X
R002b-2
X
R002b-10
X
R002b-13
GPR006-4
QA Audit R002b-10
X
X
Brief Maintainability Analysis
• Recommended Spare Parts: fuses, connectors,
wires, full boards
• Troubleshooting scenarios in User’s Manual
using parts in Maintenance Manual
▫ How to replace a blown fuse
▫ Reset buttons on system boards
▫ Reprogram OBPP/ESS microcontrollers
Brief Manufacturability Analysis
• All components listed on Bill of Materials can be
purchased from at least two independent
suppliers.
• Critical components are identified and
tolerances of these components are considered.
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RTSS resistor to set activation temperature
Voltage threshold for cell balancing algorithm
Resistors to manage the bypass loop
Components for fuel gauge algorithm -> NOT
critical (only used for general measurements)
Reliability Analysis
• Accomplishments
▫ Simplified schematic of
OBPP board to be used for
analysis
▫ MTBF of each isolated
component
SIMPLIFIED OBPP CIRCUIT BOARD
Fuse
257
Series
Blade
Fuse
Power
OP-Amps
Bypass
mechanisms
(resistor + BJT)
TLC2254
TLC2254
Voltage
Regulator
TLC2254
+12V
• Upcoming tasks
▫ MTBF for Temperature
Sensor
▫ Determine failure criteria
▫ Calculate overall MTBF
TLC2254
LM2936
+5V
Temp.
Sensor
ATMEGA 16
+5V
Optoisolator
TC1023
μprocessor
6N135
(OptoIsolator)
HV
Presentation Outline
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Introduction
Project Goals
One Board Per Pack
ESS Controller Board
System Communication
Mechanical Design
ATP / Requirements Analysis
Budget
Schedule
Budget
$418.86
$257.70
$1915.85
$208.60
$198.99
ESS
OBPP
Wiring
Hardware
Remaining Budget:
Budget – With
14
Added
OBPPs
$111.95
$198.99
$208.60
$418.86
ESS
OBPP (scaled)
$2061.60
Wiring
Hardware
Remaining Budget:
Presentation Outline
•
•
•
•
•
•
•
•
•
Introduction
Project Goals
One Board Per Pack
ESS Controller Board
System Communication
Mechanical Design
ATP / Requirements Analysis
Budget
Schedule
Schedule
• We made several complete design changes which
caused us to stray from the initial schedule.
• Initial schedule was incredibly vigorous and less
reasonable.
• Current schedule is more reasonable, but we
have still fallen behind due to redesigns of the
OBPP and fine-tuning our stand-alone
operation.
Most of schedule slip
occurred because design
took longer than expected.
Questions?
• Thank you for your attention.