Transcript Lecture Slides - UTK-EECS

Gate Drive Design of Wide Bandgap
Semiconductors for Voltage Source
Converter Applications
Zheyu Zhang
For ECE 620 – CURENT Course
September 23, 2015
What is a Gate Driver

Gate driver is a link between world of control and world of power
 World of control is world of 1.8V, 3.3V, 5V……
 World of power is world of thousands of Volts and thousands of Ampers

A good gate driver is not NICE to have, it is a MUST
2
Outline
I.
Gate Driver for Wide Bandgap Power
Semiconductors
 Gate Driver Fundamentals
 Main Functions of a Gate Driver
 Basic Functional Blocks of a Gate Driver
 Gate Driver Related Characterization of Power
Semiconductors
 Gate Driver Design Basics
 Protection for Voltage Source Converter Applications
 Summary and Key Message
3
Outline
I.
Gate Driver for Wide Bandgap Power
Semiconductors
 Gate Driver Fundamentals
 Main Functions of a Gate Driver
 Basic Functional Blocks of a Gate Driver
 Gate Driver Related Characterization of Power
Semiconductors
 Gate Driver Design Basics
 Protection for Voltage Source Converter Applications
 Summary and Key Message
4
Fundamentals of a Good Gate Driver
Static requirement


Keep the switch in ON state

Minimize ON state voltage and corresponding conduction losses
Safely keep the switch in OFF state

Minimize leakage current

Prevent spurious change of the switch state due to external or internal
disturbances
Dynamic requirement

Drive the switch from ON to OFF and OFF to ON state, with

Low switching losses

Acceptable EMI

Low commutation over-voltage
Protection (Advanced function)

Protect the switch in case of any hazardous situation

Over-current

Over-voltage

Over-temperature
5
Basic Functional Blocks of a Gate Driver
 Function of each gate driver block
 Gate driver IC & Buffer: switch the power device with sufficient driving capability
 Signal Isolator: provides galvanic isolation between the control loop and power loop
 Isolated Power Supply: power secondary side of isolator, gate driver IC & buffer
6
Gate Driver for Wide Band-gap Switches
 Wide band-gap vs. Silicon




High breakdown electric field
High doping density
High drift velocity
High thermal conductivity
 Wide band-gap switches vs. Silicon switches




High breakdown voltage → High voltage application
Small ON state resistance
→ High dv/dt, di/dt, more parasitic ringing
Fast switching speed
Small thermal resistance → High operation temperature
 Special requirements of gate driver for wide band-gap switches



High galvanic isolation capability
High common mode transient & ringing immunity capability
High operation temperature capability
7
Outline
I.
Gate Driver for Wide Band-gap Power
Semiconductors
 Gate Driver Fundamentals
 Gate Driver Related Characterization of Power
Semiconductors
 Static Characteristics
 Dynamic Characteristics
 Gate Driver Design Basics
 Protection for Voltage Source Converter Applications
 Summary and Key Message
8
Static Characteristics
 Output characteristics
 Minimize the on-state voltage drop and conduction loss
• VCC = 15 V
for Si
• VCC = 20 V
for SiC
 Gate voltage maximum ratings

Control gate-source voltage within the required range
Type
Manufacturer
Model
Gate voltage maximum ratings
Si MOSFET
Microsemi
APT34M120J
+30 V / -30 V
SiC MOSFET
CREE
C2M0080120D
+25 V / -10 V
9
Switching Commutation — Load Current Flows In
Ac
current
source
 If current flows into middle point
 Commutation between lower
switch & upper diode
 Upper switch operates as a
synchronous switch
10
Switching Commutation — Load Current Flows Out
Ac
current
source
 If current flows out of middle point
 Commutation between upper
switch & lower diode
 Lower switch acts as a
synchronous switch
11
Equivalent Circuit of Switching Commutation
Load current flows out of the middle point
Load current flows into the middle point
 Switching performance is impacted by
 Power semiconductors
 Gate driver
12
 Operating Conditions
Dynamic Characteristics
 Power semiconductors
 Gate driver
 Crss: Miller capacitance (i.e., Cgd)
 Ciss: input capacitance
(i.e., sum of Cgd & Cgs)
 Coss: output capacitance
(i.e., sum of Cgd & Cds)
 Rg(in): internal gate resistance of
device
 Vth: threshold voltage
 gfs: transconductance
 Rg(ext): external gate resistance
 Rg(dr): internal resistance of gate
driver
 Vdr: output voltage of gate driver
 Operating conditions
 Vdc: dc bus voltage
 IL: inductive load current
 Tj: junction temperature
13
Outline
I.
Gate Driver for Wide Band-gap Power
Semiconductors
 Gate Driver Fundamentals
 Gate Driver Related Characterization of Power
Semiconductors
 Gate Driver Design Basics
 Gate Driver Configuration
 Gate Driver Isolations
 Gate Driver IC & Gate Resistor
 Case Study
 Protection for Voltage Source Converter Applications
 Summary and Key Message
14
Gate Driver Configuration
 Gate driver mainly consists of
 Signal isolator  Isolated PS  Gate driver IC  Gate resistor  Decoupling cap
15
Signal Isolator
 Isolate the ground of micro-controller and gate driver IC and safely transfer
the control and error signal from the input to the output of the gate driver
Micro-controller
Gate driver IC
Selection criteria:
 Galvanic isolation capability: greater than voltage rating of power switches
 CM transient immunity: greater than dv/dt during switching transients
 Maximum/minimum frequencies: cover required switching frequency range
 Propagation delay: determined by switching frequency & control accuracy
Galvanic isolation
CM transient immunity
Minimum frequency
> 1500 V
Propagation delay
> 50 kV/µs Input to output capacitance
0 Hz (DC)
Maximum frequency
16
< 100 ns
1..10 pF
10 kHz…1MHz
CM Transient Immunity for Signal Isolator
 CM transient immunity: source & effects

Switching transitions cause high
dv/dt across the signal isolator
Coupling capacitances offer the
parasitic paths
dv/dt coupled through the parasitic
paths leads isolator to lose control by
inadvertently triggering a function or
causing false feedback.


 Typical dv/dt for wide bandgap switches



SiC discrete switch (CREE CMF20120D): ~ 30 kV/µs
SiC power module (CREE CPM212000025B): ~ 80 kV/µs
GaN transistor (Transphorm TPH3006PD): ~ 140 kV/µs
 Commercial available signal isolator
Types
Opto-coupler
Magnetically-coupler
Capacitive-coupler
CMTI
30 kV/µs
35 kV/µs
50 kV/µs
17
Isolated Power Supply
 Power supply is the “gas tank” of a gate driver.
 Provides necessary voltage for operation of the gate driver circuits
• Signal isolator
 Provides necessary voltage for driving the switch into ON and OFF
state
• The output stage supply
Selection Criteria:
 Galvanic isolation capability: greater than voltage rating of power switches
 CM transient immunity: greater than dv/dt during switching transients
 Output power: greater than power dissipation by secondary side of signal
isolator, gate driver IC, and output stage
𝑷𝒐𝒖𝒕 > 𝑷𝒊𝒔𝒐 + 𝑷𝒈𝒅 + 𝑷𝒔𝒘
(1)
𝑷𝒔𝒘 = (𝑽𝑪𝑪 − 𝑽𝑬𝑬 ) × 𝑸𝒈 𝒇𝒔 (2)
Piso: power dissipated by secondary side of isolator, obtained from the datasheet of the isolator
Pgd: power dissipated by gate driver IC, obtained from the datasheet of the gate driver IC
Psw: power dissipated during switching transition, calculated by (2)
VCC / VEE: positive/negative output voltage of gate driver IC
Qg: gate charge, obtained from the datasheet of the power device
 Output voltage: static & dynamic requirements, maximum ratings
18
Output Voltage for Isolated Power Supply
 Static requirement
 Minimize ON state resistance and conduction losses
• VCC = 15 V
for Si
• VCC = 20 V
for SiC
 Safely keep power switches in OFF state
• Minimize leakage current
• Sufficient margin to prevent spurious change of switch state due to
the external or internal disturbance
 Dynamic requirement
 Fast turn-on and turn-off power switches
 Maintain sufficient margin to not exceed gate voltage maximum ratings
of power switches
19
Gate Driver IC
 Gate driver IC is the “engine” of a gate driver.
 Provides necessary voltage for
driving the switch into ON and
OFF state
 Provides sufficient current to
charge and discharge the
switch input capacitance
 Provides low impedance loop
with quick response for fast
switching
Selection criteria:
 Operating voltage range: greater than VCC - VEE
 Peak source / sink drive current: greater than 𝑉𝐶𝐶 − 𝑉𝐸𝐸 𝑅𝑔
 Propagation delay: determined by switching frequency & control
accuracy
20
Gate Driver IC (cont’d)
Selection criteria (cont’d):
 Rise / fall time of gate driver IC output voltage: shorter than
switching delay time
 On state resistance of
S1 and S2: smaller than
desired gate resistance
21
Gate Resistor
 Gate resistor is the “gas pedal” of a gate driver, controlling the
speed of switching transients.
 Different turn-on & turnoff gate resistance
Selection criteria:
 Resistance
• Datasheet
• Analytical calculation
• Finally, tuned by set of
experiments
 Power rating
𝑷𝑹𝒈 = (𝑽𝑪𝑪 − 𝑽𝑬𝑬 ) × 𝑸𝒈 𝒇𝒔
22
Decoupling Capacitor
 Decoupling capacitor is the “fuel
injector” of the gate driver, providing
the current pulse during switching
transients
Selection criteria:
 Voltage ratings: 𝑽𝑪𝟏 > 𝑽𝑪𝑪 𝑽𝑪𝟐 > |𝑽𝑬𝑬 |
 Capacitance:
𝑪𝟏 > 𝑸𝒈 ∆𝑽𝑪𝑪
𝑪𝟐 > 𝑸𝒈 ∆𝑽𝑬𝑬
 Types: ceramic (low equivalent series inductance)
23
Outline
I.
Gate Driver for Wide Bandgap Power
Semiconductors
 Gate Driver Fundamentals
 Gate Driver Related Characterization of Power
Semiconductors
 Gate Driver Design Basics
 Gate Driver Configuration
 Gate Driver Isolations
 Gate Driver IC & Gate Resistor
 Case Study
 Protection for Voltage Source Converter Applications
 Summary and Key Message
24
Gate Driver Design — Case Study
Parameters of device under evaluation
Model
Voltage rating
Current rating
Rds(on)
C2M0080120D
1200 V
20 A @ 100oC
80 mΩ
1. Signal Isolator 2. Isolated PS 3. Gate driver IC
4. Gate resistor 5. Decoupling capacitor
25
Gate Driver Design — Signal Isolator
 Signal isolator
 Galvanic isolation capability: > 1200 V [based on datasheet]
 CM transient immunity: > 50 V/ns [based on datasheet]
Fall time
Rise time
18.4 ns
13.6 ns
dv/dt (on)
dv/dt (off)
35 V/ns
47 V/ns
Test
conditions
VDD = 800 V
ID = 20 A
 Maximum/minimum frequencies: > 100 kHz [based on applications]
 Propagation delay: < 100 ns (1 % of minimum switching period)
 Transformer based isolator ADuM 5240 is selected
Insolation voltage
2500 Vrms
Maximum frequency
1 MHz
CM transient immunity
35 V/ns
Propagation delay
< 75 ns
Secondary side power dissipation
13 mW
26
Gate Driver Design — Isolated PS
Isolated power supply
 Galvanic isolation capability: > 1200 V [based on datasheet]
 CM transient immunity: > 50 V/ns [based on datasheet]
 Output voltage: 20 V to -5 V [based on datasheet]
 Output power: > 0.159 W [based on datasheet and applications]
𝑷𝒐𝒖𝒕 > 𝑷𝒔𝒘 + 𝑷𝒊𝒔𝒐 + 𝑷𝒈𝒅 (1)
VCC
20 V
VEE
𝑷𝒔𝒘 = (𝑽𝑪𝑪 − 𝑽𝑬𝑬 ) × 𝑸𝒈 𝒇𝒔 (2)
-5 V
Qg
49.2 nC
fs
100 kHz
Piso: power dissipated by secondary side of isolator
13 mW
Pgd: power dissipated by gate driver IC
23 mW
Psw: power dissipated during switching transition, calculated by (2)
123 mW
 Traco power THB 3 series DC/DC converter is selected
Isolation voltage
3000 Vrms
Input-Output capacitance
13 pF
Power
3W
Output voltage
24 V / 5 V
27
Gate Driver Design — Gate Drive IC
Gate drive IC
 Operating voltage range: > (VCC - VEE) = 30 V [based on datasheet]
 Peak source / sink drive current:
= (VCC - VEE)/Rg < (VCC - VEE)/Rg(in) = 6.5 A [based on datasheet]
 Propagation delay: < 100 ns (1 % of minimum switching period)
 Rise / fall time of the output voltage of gate driver IC:
< min (td(on), td(off)) = 12 ns [based on datasheet]
 Pull-up / pull-down resistance: < Rg(desire) or << Rg(in) = 4.6 Ω
Rg(in)
4.6 Ω
td(on)
12 ns
td(off)
23.2 ns
Ciss
950 pF
 IXYS IXDN_609 gate driver IC is selected
Operating voltage
4.5 V to 35 V
Peak source/sink
current
9A
Rise / fall time
7 / 5 ns (@ 1.5 nF)
Propagation delay
40 ns (@ 25 V)
Pull-up / pulldown resistance
0.5 / 0.33 Ω (@ 25 V)
Quiescent power
dissipation
23 mW
(@ 20 oC)
28
Gate Driver Design — Gate Resistor
Gate resistor
 Resistance: based on datasheet and finally tuned by set of
experiments
 Different turn-on & turn-off gate resistance
 Using diode
 Usually, turn-off gate resistance is smaller than turn-on
 Power rating: > 0.123 mW [based on datasheet and applications]
𝑷𝑹𝒈 = (𝑽𝑪𝑪 − 𝑽𝑬𝑬 ) × 𝑸𝒈 𝒇𝒔
VCC
20 V
VEE
-5 V
Qg
49.2 nC
fs
100 kHz
 It is preferred to use several gate resistors in parallel to tune the
resistance
29
Gate Driver Design — Decoupling Capacitor
Decoupling capacitor
Voltage ratings [based on datasheet]
𝑽𝑪𝟏 > 𝑽𝑪𝑪 = 𝟐𝟎 𝑽
𝑽𝑪𝟐 > |𝑽𝑬𝑬 | = 𝟓 𝑽
Capacitance [based on datasheet]
𝑪𝟏 > 𝑸𝒈 ∆𝑽𝑪𝑪 = 𝑸𝒈 (𝒌𝑮𝑺 × 𝑽𝑪𝑪 ) = 𝟎. 𝟐𝟒𝟔 𝝁𝑭
𝑪𝟐 > 𝑸𝒈 ∆𝑽𝑬𝑬 = 𝑸𝒈 (𝒌𝑮𝑺 × 𝑽𝑬𝑬 ) = 𝟎. 𝟗𝟖𝟒 𝝁𝑭
VCC
20 V
VEE
-5 V
Qg
kGS: Gate voltage ripple coefficient during switching transient
Types: surface mount ceramic capacitor
30
49.2 nC
1%
Outline
I.
Gate Driver for Wide Bandgap Power
Semiconductors
 Gate Driver Fundamentals
 Gate Driver Related Characterization of Power
Semiconductors
 Gate Driver Design Basics
 Protection for Voltage Source Converter Applications

Cross-Talk

Over-Current
 Summary and Key Message
31
Mechanism Causing Cross-Talk (Turn-On)
Lower switch as the device under test
Lower switch turned on,
Vds_H rises
Displacement current 1
from Cgd_H
Current 1 flows into gate loop (2)
& Cgs_H (3), inducing +Vgs_H
If positive Vgs_H > Vgs(th)
Excessive switching losses
Generate shoot through current 4
32
Mechanism Causing Cross-Talk (Turn-Off)
Lower switch as the device under test
Lower switch turned off,
Vds_H falls
Displacement current 1
from Cgd_H
Current 3 flowing into
Cgs_H induce -Vgs_H
If negative Vgs_H < Vgs_max(-) *
Overstress the upper switch
* Vgs_max(-) refers to maximum negative biased
gate voltage required by power device itself.
33
Cross-Talk for WBG Switches (SiC as an Example)
Characteristics of Several Comparable Si / SiC Power Devices
Type
Manufacturer
Si IGBT
IR
Si MOSFET
Microsemi
SiC MOSFET
CREE


VDS / ID
(100 oC)
Qgs
Vgs(th)
(25 oC)
Vgs_max(-)
IRGP20B120U 1200 V / 20 A
169 nC
4.5 V
-20 V
APT34M120J
1200 V / 22 A
560 nC
4.0 V
-30 V
C2M0080120D 1200V / 20 A
49.2 nC
2.2 V
-10 V
Model
Properties of high voltage SiC devices

Faster switching speed

Lower threshold voltage

Lower maximum allowable negative gate voltage
SiC devices in a phase-leg configuration are easily affected by crosstalk, leading to
 Extra switching losses & reliability issues
34
Basic Ideas for Cross-Talk Suppression

To suppress cross-talk, we need to minimize spurious Vgs_H
 Reduce gate loop impedance during the switching transient
• Gate impedance regulation (GIR) assist circuit
 Pre-charge the gate-source capacitance before the switching transient
• Gate voltage control (GVC) assist circuit
Turn-on transient of lower switch as an example
35
Gate Impedance Regulation (GIR) Assist Circuit
Gate Impedance Regulation (GIR) assist circuit

Logic signals
Compared with conventional gate driver, GIR assist circuit adds
• One auxiliary transistor (Sa_H or Sa_L) in series with one capacitor (Ca_H or Ca_L)
for each device in a phase-leg.
36
Operating Principle of GIR Circuit (Turn-On)
Lower switch as the device under test
Lower switch turned on; Sa_L
remained off; Sa_H turned on
Lower switch
Ca_L disconnected
Turn-on performance of lower
switch not affected
Upper switch
Ca_H connected; gate impedance
of the upper switch minimized
Cross-talk mitigated; turn-on
energy loss reduced
37
Operating Principle of GIR Circuit (Turn-Off)
Lower switch as the device under test
Lower switch turned off; Sa_L
remained off; Sa_H remained on
Lower switch
Ca_L disconnected
Turn-off performance of lower
switch not affected.
Upper switch
Ca_H connected; gate impedance
of the upper switch minimized
Cross-talk mitigated; negative
spurious gate voltage minimized
38
Parameter Design Criterion
Simplified equivalent circuit of upper switch
during switching transient of lower one
Spurious gate voltage &
auxiliary capacitor voltage
 To avoid cross-talk



Spurious gate voltage ∈ (𝑉𝑔𝑠_max(−) , 𝑉𝑔𝑠(𝑡ℎ) )
∆𝑉+ + |∆𝑉− | ≤ 𝑉𝑔𝑠 𝑡ℎ − 𝑉𝑔𝑠_max(−) , where ΔV+ & ΔV- are related to C
𝑉𝑔𝑠_𝑚𝑎𝑥(−) + ∆𝑉− ≤ 𝑉2 (𝑖. 𝑒. , 𝑉𝐸𝐸 ) ≤ 𝑉𝑡ℎ − ∆𝑉+
where ∆V+, ∆V-, and V2 refer to positive spurious gate voltage, negative spurious gate
voltage, and negative turn-off gate voltage, respectively. C is the auxiliary capacitor
39
GIR Assist Circuit Design — Case Study
Parameters of device under evaluation
Cgd
13 pF
Cgs
1900 pF
Vgs(th)
2.5 V
Vgs_max(-)
-5 V
Vdc
800 V
aON*
27 V/ns
Rg(in)
5Ω
aOFF*
23 V/ns
Selection ranges of C
* determined
according to
test results.
Selection ranges of V2
40
Turn-on Transient of the Lower Switch
8.4% ↑
7.5% ↑
9.7% ↑
6.7% ↓
8.3% ↓
10.6% ↓
[1] Zheyu Zhang, “Active gate driver for cross talk suppression of SiC power devices in a
phase-leg configuration”, in Proc. IEEE Trans. Power Electronics, vol. 29, no. 4, 2014.
41
Turn-on Transient of the Lower Switch (cont’d)
Total Eon reduction
13.0% ↓
15.9% ↓
19.4% ↓
42
6.3% ↓
7.6% ↓
8.8% ↓
Turn-off Transient of the Upper Switch
43
Outline
I.
Gate Driver for Wide Bandgap Power
Semiconductors
 Gate Driver Fundamentals
 Gate Driver Related Characterization of Power
Semiconductors
 Gate Driver Design Basics
 Protections for Voltage Source Converter Applications

Cross-Talk

Over-Current
 Summary and Key Message
44
Short Circuit Modes & Causes
Arm Short Circuit Transistor or diode destruction
S1
S3
Series Arm Short Circuit Faulty gate drive signal
S5
S1
S3
S5
ia
ia
ib
DC
ib
DC
ic
S2
S4
ic
S6
S2
Short in LoadMiswiring or load short circuit
S1
S3
S4
S6
Ground FaultMiswiring or dielectric breakdown
S1
S5
S3
S5
ia
ia
ib
DC
ib
DC
ic
ic
S2
S4
S2
S6
[1]:Fuji IGBT modules application manual, 2004.
45
S4
S6
Fault Type-Hard Switching Fault (HSF)
 HSF--Short circuit fault at turn-on switching transient
vin
Lσ
C1
vshort
Short Circuit
Control Switch
iL
vshort
g1
Gate Driver
L
Vcc
Vee
e1
vge
Vth
Fault
inductance
Vee
ic
vin
Gate Driver
E1C2
Cdc
Vdc
ic
+
Rg g2
+
vce
vge
Vdc
vce
Kelvin Emitter e2
E2
Power Emitter
t
Hard switching fault circuit and related waveforms
46
Fault instant
Fault Type-Fault Under Load (FUL)
 FUL--Short circuit fault during the on-state condition
vin
Lσ
C1
vshort
Short Circuit
Control Switch
iL
vshort
g1
Gate Driver
L
Vcc
Vee
e1
Vee
ic
Rg
Gate Driver
Gate and
fault
current
spike
Vth
Fault
inductance
vin
vge
E1C2
Cdc
Vdc
ic
+
g2
+
vce
vge
Vdc
vce
Kelvin Emitter e2
E2
Power Emitter
t
Fault under load circuit and related waveforms
47
Fault instant
Fault Type - Example
 A protection circuit (e.g., desaturation protection) should be
activated within the short circuit withstand time tsc
HSF & Tj = 25 oC
FUL & Tj = 25 oC
Gate voltage spike
tsc=12 μs
vgs (10 V/div)
tsc=11.5 μs
vgs (10 V/div)
id (66 A/div)
id (66 A/div)
vds (200 V/div)
vds (200 V/div)
vpt (10 V/div)
vpt (10 V/div)
t (5 us/div)
t (5 us/div)
Test Condition: Vgs = +20/-2V, Vdc = 600 V, CREE 1G SiC MOSFETs (1200 V / 24 A)
48
IGBT Desaturation Protection
 Under steady-state conduction, IGBT operates in saturation
region
 Under short circuit condition, IGBT operation point moves from
saturation region to active region, so-called “Desaturation” or
150
“Desat”
12V
Typical IGBT output
characteristics
140

Vce 
 A short circuit
protection can be
triggered by the
increased
collector-emitter
voltage Vce
11.5V
120
Collector Current Ic (A)
Ic 
Saturation
Region
Active
Region
11V
10.5V
100
10V
9.5V
80
9V
60
8.5V
8V
40
7.5V
7V
20
0
6.5V
6V
0
1
2
3
4
5
6
7
Collector Emitter Voltage Vce (V)
49
8
9
10
Desaturation Protection for SiC MOSFET
Challenges :
 Commercial IGBT/MOSFET gate drivers usually have slow fault response
time (>3 μs) versus short short-circuit withstand time (SCWT) of SiC
devices
SCWT tsc (us)
Critical Energy Ec (J)
5
20
4.5
18
4
16
3.5
3
2.5
2
14
CREE_2G_Critical Energy
12
ROHM_Critical Energy
10
CREE_1G_SCWT
8
CREE_2G_SCWT
6
1.5
4
1
2
0.5
0
300
400
500
600
DC Voltage Vdc (V)
700
50
800
CREE_1G_Critical Energy
ROHM_SCWT
Desaturation Protection for SiC MOSFET
Challenges (cont’d):
 Protection threshold for SiC MOSFETs is not straightforward due to
unclearly defined active region
140
Vgs = 20 V
--- 25 °C
— 150 °C
120
Output characteristics
Drain Current Id (A)
100
80
60
N
40
20
0
M: Operating point
N: Protection point
M
0
2
4
6
8
10
12
Drain Source Voltage Vds (V)
51
14
16
18
20
Blanking Time vs. Noise Immunity
Challenges (cont’d):
 The noise immunity and fault response time become sharp contradictions
Buffer Output
Vds
id Cj
Dss
Vds
d
Ij
Rsat1
Rsat2
+
Rg g
+
vds
Rdg
Mdg
s
Comparator
+
Vdesat_th
Cblk
vgs
-
Dblk
Vdesat
-5V
 Protection circuit can be falsely triggered due to high dv/dt during turnon/turn-off transients
 Large Cblk/Cj, large Rsat2 could more effectively suppress the impact of
dv/dt on Vdesat, while blanking time will increase
52
Blanking Time Setting
Solution
 Reduction of fault response time with acceptable noise immunity
capability so that fault response time << short-circuit withstand time
Buffer Output
Dss Rsat1
id
Buffer
Vcc
d
Rsat2
Buffer Output
DESATAURATION DETECTION
Vdesat
+
Rg
g
vds
+
Gate Drive
Input PWM
Cblk
Dblk
Rdg
Mdg
-
+
Vdesat_th
vgs
s
Vee
Comparator
-5V
LOGIC CONTROL
Gate Voltage
Clamping
&
Soft Turn-off
D1 D3 D5
S1 Rs1
S2 Rs2
Manual Shunt-Down/
Fault Current Evaluation
Gate Drive Input PWM
R Rr
D2 D4 D6
Fault Report
Protection Mode Control
-5V
 Blanking time is determined by the RC network (Rsat1, Rsat2, and Cblk) :
 The blanking time is: tblk   ln
Vcc
,   Rsat1  Rsat 2   Cblk
Vcc  Vdesat _ th
 Blanking time tblanking > Turn-on switching time ton
Z. Wang, X. Shi, Y. Xue, L.M. Tolbert, F. Wang, B.J. Blalock, “Design and Performance Evaluation of Overcurrent Protection
Schemes for Silicon Carbide (SiC) Power MOSFETs”, IEEE Transactions on Industrial Electronics, Volume: 61 , Issue: 10,
Publication Year: 2014, Page(s): 5570 - 5581
53
Desaturation Technique – Testing Results
Vdc = 750 V, 200 oC, Vgs = +20/-2V, Blanking time:100 ns, CREE 2G SiC MOSFET
Hard Switching Fault
Drain-Source Voltage
(200 V/div)
Drain-Source Voltage
(200 V/div)
Drain Current
(50 A/div)
Drain Current
(50 A/div)
Threshold:5 V
t1
Fault Under Load
Capacitor Voltage
t2 t3 (5 V/div)
Gate Voltage
(10 V/div)
Threshold:5 V
Capacitor Voltage
t1 t2 t3(5 V/div)
t (200 ns/div)
 Total response time: 195 ns
Gate Voltage
(10 V/div)
t (200 ns/div)
 Total response time: 85 ns
 Blanking time delay (t1~t2): 20 ns
 Comparator response delay (t2~t3):
65 ns
 Blanking time delay (t1~t2): 130 ns
 Comparator response delay (t2~t3):
65 ns
54
Outline
I.
Gate Driver for Wide Bandgap Power
Semiconductors
 Gate Driver Fundamentals
 Gate Driver Related Characterization of Power
Semiconductors
 Gate Driver Design Basics
 Protections for Voltage Source Converter Applications
 Cross-Talk
 Over-current
 Summary and Key Message
55
Summary & Key Message

No power conversion without power semiconductors

Power semiconductors is NOTHING without a gate
driver!
 The gate driver will properly drive a power semiconductor
and bring the maximum performance. For WBG devices,
• Driving capability of gate driver IC (rise/fall time, pull-up/pull-down
resistance) & CM transient immunity of gate driver isolation are
special requirements.
 The gate driver will protect a power semiconductor and
entire converter if something goes wrong. For WBG devices,
 Cross-talk is easily induced, leading to potential hazard of shootthrough failure and gate terminal reliability issues. A gate assist
circuit was introduced for cross-talk suppression.
 Short circuit capability is limited. The desaturation protection circuit
with < 200 ns response time was described for device reliability
enhancement.
56
57