Transcript Platform-Based Mixed Signals Design in Picoradio Baseband

Yanmei Li,
Fernando De Bernardinis,
Alberto Sangiovanni-Vincentelli ,
Jan Rabaey
Platform-Based Mixed Signal Design in
Picoradio Baseband Design Exploration
http://chess.eecs.berkeley.edu
Abstract
Baseband Circuit Design
Analog Platforms have been exploited for system
level analog and also mixed-signal design, which allow
effective co-design of analog and digital components. A
platform-based mixed signal design is presented, which
is the baseband of the Picoradio receiver for wireless
sensor networks. The basic constraint for this design is
the very stringent power consumption. Using platforms
consisting of Anadigm FPAA and Xilinx FPGA, we
developed a mostly-analog solution as an alternative to
the mostly digital baseband. The FPAA/FPGA prototype
successfully demonstrated how different tradeoffs
between analog and digital could be exploited to
implement the Picoradio baseband. Also, we will present
our low-power sub-threshold circuit design which
implements the mostly-analog baseband prototype.
Sig_in

Ref_in
S&H
Sync
R2
Sclk

Sig
R1
0.1

T&H
Rcs
CS
Samp_thresh
• 500kHz clock
• Tolerable kickback
noise
CS_Level
Mostly-Analog Solution of Picoradio Baseband
OTA-C Integrator Design
 Symmetrical OTA topology
BB1
RF
RF Filter
MEMS
BB1 Ref
LNA
BB2
RF
MEMS
 Tune Gm of OTA easily
Env
Det
Env
Det
 Integration output can not keep constant for
?
BB2 Ref
20us (required by the algorithm) without the
cascaded structure
 Long channel low-leakage transistors here
Integration-delay based synchronization
dvc (t )
i
G v (t )
 c  m in
dt
Cintg
Cintg
Searching
Input
R2
Integration
Window
With Josie Ammer,
Brian Otis
November 18, 2004
 Programmable fabric for prototype
 FPGA (Xilinx VirtexE600)
 FPAA (Anadigm 221)

Co-simulation results:
 Modeled
Reset level ~200mV
 Source degeneration resistor
Symbol Start
R2
Integration
Window
 Integration cap. is reset to a separate branch

R1
Integration
Window
Synched
 Cap. ~20pF  desirable integration constant
Gm matching for 0.1*Vin and Vin
Power consumption ~22uW
R1
Integration
Window
and simulated in Simulink
 Mapped to programmable platforms
 Analog : filters, integrators,
comparators and OpAmps are
automatically mapped onto the
FPAA
 Digital : the StateFlow FSM is
automatically mapped onto the
FPGA with the ST2VHD flow and
Xilinx backend
 1V power supply
 Sub-threshold design
 Verified by co-simulation

Synchronization needs ~30 symbols
Offset tolerance (e.g. when Vin=20mV,
offset=5mV can be tolerated)

 Total power (Analog+Digital) ~180uW