Electronics_for_CEDAR_May_2012 - Indico

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Transcript Electronics_for_CEDAR_May_2012 - Indico

Electronics for CEDAR
Cristina Lazzeroni, Marian Krivda, Richard Staley, Xen Serghi, Karim Massri
University of Birmingham, UK
3/5/2012
1
CEDAR PMT Socket Production
1 PMT socket uses 2 PCB discs.
Made as a panel of 8 ‘discs’:
Dynode bias resistors
+ coupling capacitors
Populate
Both sides
Pop-out &
Assemble
R.Staley, CEDAR UK Meeting - Liverpool - 3rd May 2012
2
CEDAR PMT Socket Production
As of Mid-day 1st May 2012 - 20 panels populated on 1 side.
(Simon Pyatt)
PMT socket tested before handing over to Liverpool University
Ohmmeter to check resistor bias network
Multimeter to check capacitors
High voltage power check
R.Staley, CEDAR UK Meeting - Liverpool - 3rd May 2012
3
CEDAR PMT Socket Timescales
For 128 Sockets
Assembled at Birmingham
Design - Done
x
Order Components
x
Layout at Birmingham
x
PCB Production
x
Mar.
April 2012
19
2
26
9
16
May
23
30
7
June
14
21
28
4
11
Aug.
July
18
25
2
9
16
23
30
6
13
Engineer (rjs) effort at 50%
Technician effort at 50%
Physicist / Student
External PCB company
Design/Layout Checks with PMT
PCB Assembly - UK
Production Testing
PMT Signal Cables - Find + Make
?
32 PMT Sockets
128 PMT Sockets
+ 5% Spares
Holding item – Still to find a suitable cable
( thin, high-speed, differential, screened, LSZH )
CERN Stores (04.21.51.702.6) no longer stocked
RS , Farnell, …
R.Staley, CEDAR UK Meeting - Liverpool - 3rd May 2012
4
• All the patch panel (PP) schematics are finished
• The HV PMT PP layout is 95% finished. Will be completed next week
and will then be sent to be manufactured by PCB-Pool and be ready for
the end of May.
• The rest of the PP will follow and will be ready for June
• We are waiting for a high voltage connector from CERN for the HV
PSU PP to see if it is suitable for our needs.
• There are two options for the HV cabling from the HV PMT PP to the
Environmental Enclosure (EE) HV PSU PP.
 Option 1: have loose HV cables from the HV PMT PP grouped
together in groups of 32 and then fed to the PP in the EE.
 Option 2: have another PP mounted on the detector, per HV PMT
PP, so the HV cables are short, neat and tidy. Then connect a cable
from this PP to the HV PSU PP on the EE.
X.Serghi, CEDAR UK Meeting - Liverpool - 3rd May 2012
Option
1:
Option 2:
X.Serghi, CEDAR UK Meeting - Liverpool - 3rd May 2012
• Needs mounting holes
• Tidy up
• PCB-Pool next week. ~8 day turn around for 4 PP
• A couple of days to populate board
X.Serghi, CEDAR UK Meeting - Liverpool - 3rd May 2012
NINO board proposal ver. D
(design which allows separation of NINO inputs and outputs)
Edge facing incoming beam when folded down
8 differential inputs from PMTs
DCS connectors
(CAN bus daisy
chain)
IC 1
IC 3
SK 1
DC power input
IC 2
ELMB128-A
50mm x 67
mm
IC 4
32 NINO
Outputs to
HPTDC
IC 8
IC 6
SK 2
IC 5
IC 7
Max. 215 mm x 155 mm PCB
M. Krivda, CEDAR UK Meeting - Liverpool - 3rd May 2012
8
NINO PCB
M. Krivda, CEDAR UK Meeting - Liverpool - 3rd May 2012
9
NINO board
• 2 options for setting NINO Threshold
• Only one external power supply 7V is necessary
=> on-board regulators for analog 2.5V & 5V
• 3 separate GNDs: CAN bus, Digital, Analog
• The layer structure is:
•
•
•
•
•
•
Top Tracks
AGND Plane
Inner tracks 1
Inner tracks 2
2v5 & 5v plane
Bottom Tracks
• Ground guard rail around the NINO inputs
M. Krivda, CEDAR UK Meeting - Liverpool - 3rd May 2012
10
NINO board
analog ground and cooling
• Voltage reg. LHC4913PDU needs cooling
• AGND must be isolated from other noisy
grounds !
PowerSO-20 slug-up
The fixing hole connected to AGND
through 0 ohm resistor
AGND (Possibility to isolate/detach heatsink from detector ground ???)
M. Krivda, CEDAR UK Meeting - Liverpool - 3rd May 2012
11
NINO board
• Schematic entry and specification of
components -> done
• PCB design at RAL -> done
• Verification of design -> done
• Production -> RAL waiting for offer from 3
companies (2 options – 10 or 20 days)
• If delivery for RadTol version of components is
too long => use standard ones and replace them
later
M. Krivda, CEDAR UK Meeting - Liverpool - 3rd May 2012
12
NINO board timescale
• 10 or 20 working days for production, assembly
(RAL organizes with external company)
• 3-4 days delivery to CERN
• 4 weeks for testing
M. Krivda, CEDAR UK Meeting - Liverpool - 3rd May 2012
13
NINO test - Experimental setup
Florence preAmp/Differential
Output
TRIGGER
TDC
Passiv
e
splitter
NINO
ADC sampler
Karim
Massri –
Patch panel
NINO→TD
C
3/05/2012
14
Getting the charge from the ADC
ADC signals with amplitude > 1mV have been fitted with a Gaussian
− t − t 0 /2
V= V0e
2
2
→Q= 2 V 0 / R
Karim
Massri –
3/05/2012
15
Checking the NINO threshold
~5% losses due to a previous signal
too close (<15 ns)
[not relevant for our test]
Value obtained from NINO checkpoint
using Crispin's convertion factor
(4 mV = 1 fC)
Karim
Massri –
3/05/2012
16
Results – Florence preAmp
Pedestal
Signal
→
fit with exponential
→
fit with a polya
Minimum Affordable Threshold (MAT):
391 mV = 0.098 pC
Single Electron Response LOSS (Filled area):
~ 2.5%
MA
T
Karim
Massri –
3/05/2012
17
Results – Differential Output
Pedestal
Signal
→
fit with exponential
→
fit with a polya
Pedestal measured by ADC seems to be
greater than the one @ NINO (cfr. MAT)
→ TO BE INVESTIGATED
Minimum Affordable Threshold (MAT):
180 mV = 0.045 pC
Single Electron Response LOSS (Filled area):
~ 0.06%
MA
T
Karim
Massri –
3/05/2012
18