Transcript This is my Title - UCSB HEP - University of California, Santa Barbara

The BaBar Silicon Vertex
Tracker
Owen Long
University of California, Santa Barbara
for the
BaBar Collaboration
Owen Long, UCSB
VERTEX ‘98 Santorini, Greece
PEP-II and the BaBar Experiment
Physics Objective:
• CP violation in B meson decays.
• Overdetermine the parameters of the CKM quark mixing matrix.
Experimental Approach:
• High-luminosity e+e- collider with Upsilon(4s) center-of-mass energy.
• B and anti-B mesons produced coherently.
• CP asymmetries depend on Dt between B decays.
• Time-integrated CP asymmetries vanish.
• Measurement of B decay points is essential.
• Asymmetric beam energies boost Upsilon(4s) in lab (bg=0.56).
Upsilon(4s)
decay point
e- beam
direction
Dz
B0 decay
point
Owen Long, UCSB
VERTEX ‘98 Santorini, Greece
B0 decay
point
SVT Institutions
USA:
• Lawrence Berkeley National Laboratory
• Stanford University
• University of California, Santa Barbara
• University of California, Santa Cruz
• University of California, San Diego
Italy:
• University of Wisconsin
Owen Long, UCSB
VERTEX ‘98 Santorini, Greece
•Ferrara
•Milan
•Pavia
•Pisa
•Torino
•Trieste
SVT Design Requirements and
Constraints
Performance Requirements
• Dz resolution < 130 mm.
• Single vertex resolution < 80 mm.
• Stand-alone tracking for Pt < 100 MeV/c.
PEP-II Constraints
• Permanent dipole (B1) magnets at +/- 20 cm from IP.
• Polar angle restriction: 17.20 < Q < 1500.
• Must be clam-shelled into place after installation of B1 magnets
• Bunch crossing period: 4.2 ns (nearly continuous interactions).
• Radiation exposure at innermost layer (nominal background level):
• Average:
33 kRad/year.
• In beam plane: 240 kRad/year.
• SVT is designed to function in up to 10 X nominal background.
Owen Long, UCSB
VERTEX ‘98 Santorini, Greece
The BaBar Silicon Vertex Tracker
•
•
•
•
5 Layers of double-sided, AC-coupled Silicon.
Custom rad-hard readout IC (the AToM chip).
Low-mass design. ( Pt < 2.7 GeV/c2 for B daughters)
Stand-alone tracking for slow particles.
• Inner 3 layers for angle and impact parameter measurement.
• Outer 2 layers for pattern recognition and low Pt tracking.
20 cm
30 cm
40 cm
Owen Long, UCSB
VERTEX ‘98 Santorini, Greece
Space Frame and Support Cones
Owen Long, UCSB
VERTEX ‘98 Santorini, Greece
SVT Geometry
Layer
Radius
1
3.3 cm
2
4.0 cm
3
5.9 cm
4
9.1 to 12.7 cm
5
11.4 to 14.6 cm
Be Beam pipe
1.0 % X0
10 cm
(Arched wedge wafers not shown)
Owen Long, UCSB
VERTEX ‘98 Santorini, Greece
SVT Modules
Z-Side
High Density
Interconnect
(mechanical model)
Micro-bonds
Flexible Upilex Fanout
Micro-bonds
Phi-Side
Si Wafers
Fanout Properties:
• < 0.03 % X0
• 0.52 pF/cm
Carbon/Kevlar fiber
Support ribs
Owen Long, UCSB
VERTEX ‘98 Santorini, Greece
Ringframe Fixtures
Ringframes protect Si wafers and High Density Interconnects (HDIs) during testing.
• “Parking lot” on Fanout enables
wafer tests without bonding.
• Bonds for strips with faults plucked
before bonding to HDI.
• Fanout is cut, glued, and bonded
to HDI after wafer testing.
• 1/2 modules are tested again
before module assembly.
Owen Long, UCSB
VERTEX ‘98 Santorini, Greece
SVT High Density Interconnect
Flexible Tail (testing version)
Functions:
• Mounting and cooling
for readout ICs.
Berg
Connector
• Mechanical mounting point
for module.
Mounting
Buttons
Features:
• AlN substrate.
• Double sided.
• Thermistor for temp. monitor.
• 3 different models.
AToM
Chips
Upilex
Fanout
Owen Long, UCSB
VERTEX ‘98 Santorini, Greece
Silicon Wafers
Features:
•Manufactured at Micron.
•300 mm thick.
•6 different wafer designs.
•n- bulk, 4-8 kW cm.
•AC coupling to strip implants.
•Polysilicon Bias resistors on wafer, 5 MW.
Owen Long, UCSB
VERTEX ‘98 Santorini, Greece
Silicon Wafers
Edge
guard ring
Bias ring
Polysilicon
bias resistor
P-stop
55 mm
n+ Implant
p+ Implant
Al
50 mm
Polysilicon
bias resistor
p+ strip side
Owen Long, UCSB
VERTEX ‘98 Santorini, Greece
Edge
guard ring
n+ strip side
Measured Wafer Characteristics
Strip Properties
n-side
n-side
n-side
p-side
• Strip Pitch:
50 mm
55 mm
105 mm
50 mm
• Inter-strip C:
1.1 pF/cm
1.0 pF/cm
1.0 pF/cm
1.1 pF/cm
• AC decoupling C:
20 pF/cm
22 pF/cm
34 pF/cm
43 pF/cm
0.19 pF/cm
0.36 pF/cm
0.17 pF/cm
4 to 8 MW
4 to 8 MW
4 to 8 MW
• Implant-to-back C:
• Bias R:
4 to 8 MW
Bulk Properties
• Bias current: 0.1 to 1.0 mA
• Bulk current: 0.1 to 1.0 mA
• Depletion voltage: 35 to 45 V
Owen Long, UCSB
VERTEX ‘98 Santorini, Greece
Detector-Fanout Assemblies
Status:
• All wafers are glued to fanouts, bonded, and tested.
• Over 0.3 million bonds.
Fault Types:
• Pinhole - Break in the AC coupling capacitor, short between metal and implant.
• P-stop short (DC) - Bond foot breaks through oxide layer shorting metal and p-stop.
• High current (DC) - Low value for bias resistor.
• Unbondable - Damaged or obstructed bond pad, rework not possible.
Fault
Channels
Pinhole
DC-fault
Other
1-2%
1-2%
1%
Total faults:
2-4%
Owen Long, UCSB
VERTEX ‘98 Santorini, Greece
The AToM Chip
AToM = A Time Over threshold Machine
Custom Si readout IC designed for BaBar by:
• LBNL
• INFN-Pavia
• UCSC
Owen Long, UCSB
VERTEX ‘98 Santorini, Greece
8.3 mm
Features:
•128 Channels per chip
•Rad-Hard CMOS process (Honeywell)
•Simultaneous
– Acquisition
– Digitization
– Readout
•Sparsified readout
•Time Over Threshold (TOT) readout
•Internal charge injection
5.7 mm
The AToM Chip
Si
TOT Counter
Time Stamp
Buffer
Event Time
Event Number
Buffer
15 MHz
PRE
AMP
Shaper
CAL DAC
Comp
Thresh
DAC
CINJ
Revolving
Buffer
193 Bins
Sparsification
Readout Buffer
Chan #
CAC
Serial
Data Out
Amp, Shape, Discr, Calib
•5-bit CAL DAC (0.5 fC/count)
•5-bit Thr DAC (0.05 fC/count)
•Shaping time 100 - 400 ns
Trigger Latency Buffer
•15 MHz Sample rate
•Total storage = 12.7 us
Owen Long, UCSB
VERTEX ‘98 Santorini, Greece
TOT, Tstamp, Buffering
•4 bits TOT (logarithmic)
•5 bits Hit Tstamp
(67 ns/count)
•4 buffers / channel
Procedure
• Fix charge injection value
• Scan Threshold DAC (0-63)
1 Threshold DAC count = 10.5 mV
10.5 mV/count / Gain = 0.053 fC / count
• Fit Hit efficiency vs Threshold to Error Function
Width = Noise
50% point = Offset for Qinj
Hits
Threshold Scan
Noise
Gain Measurement
• 3 threshold scans at different Qinj values
• Fit 50% point vs Qinj
• Slope is Gain (Dthr/DQ in mV/fC)
• Intercept is Threshold DAC offset
Threshold
Offset Counts
Offset
Threshold DAC
Offset
Qinj Counts
Owen Long, UCSB
VERTEX ‘98 Santorini, Greece
TOT and Charge Scan
• Scan calibration DAC (0-63) at a fixed threshold.
• Range of injected charge: 0 to 30 fC (1 MIP = 3.8 fC)
• Measure Time Over Threshold (TOT) response.
• Hit TOT stored in 4 bits (1-15).
Injected Charge (fC)
Time Over Threshold
Time Over Threshold
Injected Charge (fC)
1 MIP
1 MIP
CAL DAC
Owen Long, UCSB
VERTEX ‘98 Santorini, Greece
CAL DAC
Measured Noise and Gain
100 ns
AToM-I, test board: 450 ele + 47 ele/pF
AToM-II, test board: 350 ele + 40 ele/pF
AToM-I, Layer 2 mod:
Phi-side
Z-side
1350 ele
1050 ele
AToM-I, Gain:
190 mV/fC
200 ns
400 ns
375 ele + 45 ele/pF
275 ele + 35 ele/pF
325 ele + 39 ele/pF
225 ele + 26 ele/pF
1200 ele
850 ele
1050 ele
750 ele
235 mV/fC
AToM-II, Gain:
200 mV/fC
300 mV/fC
• Total strip capacitance ranges from 11 to 37 pF.
• Threshold setting of 4 X Noise still well below 1 MIP ( about 20,000 ele ).
Chip Properties
Threshold offset dispersion:
Chip power consumption:
14 mV or 440 ele
0.57 W/chip, 4.5 mW/chan
Owen Long, UCSB
VERTEX ‘98 Santorini, Greece
AToM-II measurements
are preliminary.
AToM IC and Wafer Characteristics
After Exposure to Radiation
AToM-I Chip
After exposure to 2.4 MRad with Co60 source
• Gain dropped 0 to 20 %
Power off during exposure
C=0
Noise Increase
dNoise/dC
15 to 80 %
15 to 50 %
Power on during exposure
C=0
5 to 10 %
dNoise/dC
< 5%
• Only 3 chips tested. Will check this result with more tests.
Silicon Wafers
After exposure to 1 MRad of photons from a Co60 source
• <17% increase in interstrip capacitance
• Current density <350 nA/cm2, mostly generation at Si - insulator surface
Owen Long, UCSB
VERTEX ‘98 Santorini, Greece
Production and Construction
• Silicon Wafers:
• All wafers in hand.
• Wafers glued to fanouts, bonded, and tested.
• Front-End Electronics:
• High Density Interconnect (HDI) substrate production nearly complete.
• 2 lots of AToM-I in hand. AToM-II testing underway.
• Several HDIs loaded, tested, and bonded to detectors.
• Mechanical:
• Support cones, space frame, and mounting rings complete.
• Ready to begin module assembly.
• Back-End Electronics:
• Production complete. Loading and testing.
• Estimated date of completion: Early March 1999.
Owen Long, UCSB
VERTEX ‘98 Santorini, Greece
PEP-II at SLAC
The PEPII Collider at SLAC
• Luminosity: 3 x 1033 to 1034 cm-2 s-1
• 30 to 100 million Upsilon(4s) per year.
• Beams collided head-on (no crossing angle).
• Bunch crossing period: 4.2 ns
• Interactions effectively continuous.
• Permanent dipole magnets required
close to interaction point.
Owen Long, UCSB
VERTEX ‘98 Santorini, Greece
SVT Mechanical Features
Brass
cooling rings
Carbon fiber
Space Frame
22 cm
B1 dipole
permanent magnet
(inside support cone)
Carbon fiber
support cones
B1 dipole
permanent magnet
(inside support cone)
109 cm
Owen Long, UCSB
VERTEX ‘98 Santorini, Greece
SVT Mechanical Features
Silicon wafers
Carbon & Kevlar fiber support ribs
Owen Long, UCSB
VERTEX ‘98 Santorini, Greece
SVT Modules
Layer
Number of
Wafers
Total Phi-Strip Length
Backward
Forward
Z-Strip Length
5b
8
26.5 cm
26.5 cm
4.1 to 5.1 cm
5a
8
26.5 cm
25.1 cm
4.2 to 5.1 cm
4b
7
22.4 cm
19.9 cm
4.2 to 5.1 cm
4a
7
22.4 cm
18.5 cm
4.2 to 5.1 cm
3
6
12.8 cm
12.8 cm
7.0 cm
2
1
4
4
8.8 cm
8.2 cm
8.8 cm
8.2 cm
4.8 cm
4.0 cm
Owen Long, UCSB
VERTEX ‘98 Santorini, Greece
Silicon Wafers
P-Stops
Features:
•Manufactured at Micron.
•300 mm thick.
•6 different wafer designs.
•n- bulk, 4-8 kW cm.
n- Bulk
n+ Implant
Readout
Pitch
•AC coupling to strip implants.
•Polysilicon Bias resistors
on wafer, 5 MW.
Aluminum
Strip
Pitch
Silicon
dioxide
p+ Implant
Owen Long, UCSB
VERTEX ‘98 Santorini, Greece
n- Bulk
Wafer Specifications
Used in Layers
1,2, and 3
Used in Layers
4 and 5
Owen Long, UCSB
VERTEX ‘98 Santorini, Greece
Phi Side Readout Pitch, 1-3
Phi side is 30 - 100 % half bonded
due to E x B effect.
• 100 to 110 mm readout pitch
where charge is spread over
more strips.
• 50 to 55 mm readout pitch
where charge is focused on
fewer strips.
Compromise between
• Hit efficiency
• Signal to noise ratio
and
• Hit resolution
• 2-Track resolution
100 mm
Pitch
Owen Long, UCSB
VERTEX ‘98 Santorini, Greece
50 mm
Pitch
SVT Data Transmission
•HDI: High Density Interconnect. Mounting fixture
and cooling for readout ICs.
•Kapton Tail: Flexible multi-layer circuit. Power,
clock, commands, and data.
Power
Supplies
•Matching Card: Connects dissimilar cables.
Impedance matching.
•HDI Link: Reference signals to HDI digital common.
Back
Cables
•DAQ Link: Multiplex control, demultiplex data.
Electrical -- optical conversion.
Front
Cables
Si Wafers
MUX
Power
HDI
Link
Matching
Card
HDI
Kapton
Tail
DAQ
Link
Fiber Optic
to DAQ
Owen Long, UCSB
VERTEX ‘98 Santorini, Greece
Calibration
Internal charge injection used for
• Measuring Gain, Noise, and Threshold Offsets
• Identifying shorts and bad channels
• Examining Time Over Threshold (TOT) response
• Testing digital functionality
Charge injection circuit
• 5-bit DAC (0-63)
• 1 DAC count = 0.48 fC
• Range 0 - 30 fC (1 MIP = 4 fC)
Calibration methods
• Threshold scan (Gain, Noise, Offsets)
• Charge scan (TOT response)
Owen Long, UCSB
VERTEX ‘98 Santorini, Greece