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JRA-1
ISRSI Consortium Meeting
Perugia, 17-01-2005
INAF/IASF (BO,PA)
This work is the preliminary activity in the framework of the development of
an Itialian hard X ray (10-80 keV) telescope based on multilayer mirrors.
The current project (funded for 6 months by the technological department of
the Italian Space Agency, ASI) foresees the production of a multilayer test
optics (OAB) and two small focal plane prototypes.
Low noise and power consumption
ASIC for CZT/CdTe pixellated detectors
Politecnico di Milano
Construction of microstrip CdTe
detector prototype
IASF/CNR – Sezione di Bologna
Construction of Pixel CZT detector
prototype
IASF/CNR – Sezione di Palermo
ASIC
Pixel
main requirements
CZT
CdTe
Microstrip
detector
(eV Products)
Dynamic
detector
ACRORAD
10 keV – 100 keV
Geometric
range
Geometric
1010 mm22
1010 mm
surface
Power
surface
1 mW/ch
Dissipation
Active area
88 mm22
Active area
88 mm
Multichannel
Thickness layout
1-2 mm
Thickness
1-2 mm
Number of
Number
256
16+16 (crossed)
pixels
strips
0.5 mm
0.5 mm
(0.45 mm
Pitch
(0.4 mm anodes,
anodes, 0.05 mm
0.1 mm gap)
gap)
Pixel detector (16x16 pixels) and connection interface
The typical dark current level at 200 V bias is 0.2-0.3 nA/pixel
Microstrip detector and connection interface
(left) Photograph of the CdTe
microstrip detector. On the opposite
surface the strip layout is the same
but in the othogonal direction; (right)
A microscopic view of the same
detector showing the bonding of
each strip obtained using brass wire
(150 µm wide) and conductive glue.
The microstrip detector mounted on a
ceramic (Al2O3) bilayer substrate. In the
vertical direction the two 8-pin connectors
for the anode readout through the ASIC
(DC coupling) are visible while in the
opposite direction are the connectors for
the cathode readout using 8+8 charge
sensitive amplifier (AC coupling)
The new ASIC for the hard x-ray focal plane
The ASIC chip was first developed for thick CdTe/CZT array detectors for use in
astrophysics applications over a wide energy range (20-2000 keV). The current
design is a modification of the original ELBA (ELettronica a BAsso rumore e
consumo) chip in which the dynamic range has been tuned to the 10-100 keV
range.
The chip can be easily tuned to the
I-V characteristics of the detector by
means of the Ipre input that modifies
the MOSFET operation current.
Technology : 0.8 m BiCMOS (AMS)
Energy Range : 10 keV – 100 keV
(CdTe-CZT)
8 channels: Charge Preamplifier +
Shaper (peaking time 1.2 s)
Power consumption : 0.5 mW/ch
ASIC tests results (I)
Output
[V]
voltage
VOUT[%]
Linearity
Error
2.6
1.0
0.8
2.4
0.6
MC8ASI1
0.4
2.2
0.2
MC8ASI1
50 keV
0.0
2.0
-0.2
20 keV
-0.4
1.8
10 keV
-0.6
1.6
-0.8
-1.0
1.4 0
100 keV
5 keV
10
0
20
1
30 40 50 60 70 80 90 100
2
3 Energy
4
5[ keV
6 ] 7
8
9
Photon
Time [ s ]
Channel vs energy linearity. The linearity of the single
channels
is better
over to
thesignals
entire simulating
energy range
Response
of anthan
ASIC0.4%
channel
(from
~5photon
keV to energies
100 keV).
various
ASIC tests results (II)
MC8ASI1
5
Equivalent
GainNoise Charge
[electrons r.m.s.]
14
12
400
4
10
8
300
3
Ch1
Ch2
Ch3
Ch4
6
4200
Ch5
Ch6
Ipre = 1 nA
Ch7
Ipre = 2 nA2
Ch8
Ipre = 5 nA
Ipre = 10 nA
10= 20 nA
Ipre
2
0
0
1
2
4
6
8
Preamplifier feedback bias current Ipre [nA]
2
3
4
5
Equivalent Noise Energy
in CdTe/CZT [keV FWHM]
500
6
7
8
Channel
TheThe
equivalent
noise
each ASIC
asofa function
ASIC gain
and(rms)
gainof
uniformity
as channel
a function
Ipre :
of the MOSFET
current
the gain uniformity
is always
better than 5%.
The ASIC board I/F with the pixel detector
To optimize the coupling with the pixel
detector and to be able to read out contiguous
subsets of pixels (at least 88) the ASICs
have been mounted on a ceramic board
containing the bias circuit and filters. The
major constraint on the design of this support
is due to the layout of the detector output pins:
the board thickness is limited to 2.5 mm and
the lateral size to 82.5 mm.
The Multiparametric back-end electronics
Multiparametric electronics (up to 128
channels) with coincidence logic. Each pixel
is connected to a separate electronic
channel. Each event above the threshold is
loaded into a de-randomisation FIFO,
converted by a flash 12 bit ADC and then a
32 bit word is generated containing for each
hit in the coincidence time window the pixel
id and the 10 MSB of amplitude (energy).
Data Handling Electronics
Gamma camera-like (16+16 channels) with position averaging. This system uses a resistor
array (the XY/Strip small box in the scheme of Fig. 6 and in the picture shown in Fig. 7) as
the interface between the detector channels and the ADC (12 bit). Each signal above a userdefined energy threshold is transmitted through the resistor array at each corner and
converted by 4 flash ADCs (Xa, Xb, Yc, Yd). The energy (10 bit) of the event is
reconstructed by summing the 4 signals, while the position coordinates (x,y) are provided by
the weighted average (10 bit) of the signals in both directions by means of:
x = (Xa – Xb)/(Xa+Xb) ; y =(Yc-Yd)/Yc+Yd)
The final reconstructed data is loaded in a 32 bit unsigned word and transmitted to the
acquisition system using an handshake protocol.
Quick-Look Analysis
Pixel Detector (CZT) Spectral Resolution
@ 60 keV
Threshold ≈ 8 keV
Resolution ≈ 4.7 %
100
Pixel Detector (CZT) Spatial resolution and
pixel cross-talk
80
60
40
20
Pixel to total events ratio (%)
89,25
0,96
0,82
2,18
1,75
1,48
1,92
0,62
0
0,99
171
172
173
187
188
Pixel
189
203
204
205
Spatial distribution of counts when the beam is collimated on a single
pixel. (right) the counts colour map of the incident and neighbouring
pixels. (left) the histogram of the pixel to total counts ratio. Almost 90% of
the photopeak (60 keV) counts are detected by the irradiated pixel.