Transcript Presentación de PowerPoint

Preliminary measurements for the
8 channel prototype of SPD
discriminator ASIC
I.
II.
III.
IV.
V.
VI.
The 8 channel prototype.
Status of the test.
Noise.
Gain.
Test plan.
Schedule for PRR and production.
LHCb Calo Electronics Meeting – December 2003 – Clermont-Ferrand
I. The 8 channel prototype (I).
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Random signal shape (20-30 phe/MIP): shaping methods discarded  integration.
Only about 80% of signal in 25 ns (no dead time for integration allowed) + response to consecutive
events  Dual channel: synchronous system + Pile-up correction
PMT gain limited by aging (DC current)  100fC/MIP in hotest cells.
5-10 MIP range to perform tail correction.
Robust to temperature variations (band gap reference).
Small cavity  Power consumption < 1W. Prototype at 3.3V (0.6 W)
I. The 8 channel prototype (II).
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Area: 30 mm2.
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Package: naked die (10),
JLCC68 (10) and EDQUAD
TQFP 64 (30).
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Target package is EDQUAD
TQFP 64 for size and power
dissipation.
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Ceramic JLCC68 is also
requested because better
knowledge of its performance
(used for previous prototypes) .
II. Status of the test.
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10 JLCC + 10 naked dies were receive at beginning of November .
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46 EDQUAD TQFP were received last week.
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Automated test system is under development.
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Hardware (test boards and VHDL code for FPGA used for DAQ) is finished.
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Software (Labview and C) for data taking and on-line analysis is almost finished.
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Digital interface has been completely tested with random sequences write/read and
is fully functional.
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Power consumption is as expected: 180 mA (0.6 W).
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Consumption of different supply pins is in agreement with simulation.
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Some further “manual” measurements have been done.
III. Noise (I): 50  PMT load (input resistor).
Differentiated Histogram Chip 1 Ch 3-1
Differentiated Histogram Chip 1 - Ch 3-2
Histogram Chip 1 Ch 3-1
Histogram Chip 1 Ch 3-2
4,00
3,00
2,00
-d<VoD>/dt [V]
1,00
0,00
-1,00
-2,00
-3,00
-4,00
-90
-85
-80
-75
-70
-65
-60
-55
Threshold [mV]
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Sigma of differential histogram between 1 and 2 mV r.m.s.
Measurement error is not negligible compared with transition width.
Possible contributions of pick-up noise should be studied.
-50
III. Noise (II): 390  PMT load (input resistor).
Differentiated Histogram Chip 1 Ch 5-1
Differentiated Histogram Chip 1 Ch 5-2
Histogram Chip 1 Ch 5-1
Histogram Chip 1 Ch 5-2
4,00
3,00
2,00
-d<VoD>/dt [V]
1,00
0,00
-1,00
-2,00
-3,00
-4,00
-100
-90
-80
-70
-60
Threshold [mV]
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Sigma of differential histogram between 1 and 2 mV r.m.s.
Noise increase is not seen.
Measurement error is not negligible compared with transition width.
Possible contributions of pick-up noise should be studied.
-50
-40
IV. Gain (I): pulse injection.
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A step pulse is differentiated through a series capacitor: the charge over RLPMT
must be Q=Cac x Vstep (Vstep is the pulse amplitude).
Cac
Vstep
1pF
RLPMT
50-400 Ohm
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The pulse must be much longer than 25ns
The time constant of the circuit <<25ns to inject all the charge in 1 period.
The 95 % of the signal is on 25 ns (gain has been corrected).
IV. Gain (II): results.
Gain for Ch 5-1
1500,000
Vth/Q C1
Threshold to 0->1 [mV]
1000,000
500,000
0,000
-1,50E+03
-1,00E+03
-5,00E+02
0,00E+00
5,00E+02
1,00E+03
1,50E+03
-500,000
-1000,000
-1500,000
Input charge [fC]
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Gain for 390  PMT load : 1mV/fC.
Linear range  1 pC of input charge or 1 V of threshold.
Input referred noise (ENC) between 1 and 2 fC.
MIP signal between 100 fC and 50 fC (after first compensation of PMT non-uniformities).
V. Test plan.
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Offset per subchannel (function of pile-up compensation subtractor).
Noise per subchannel (function of pile-up compensation subtractor and PMT
load).
Cross-talk between subchannel threshold (same Vref).
Low frequency noise (random trigger vs. sync. trigger).
Linearity (function of pile-up compensation subtractor).
Matching and calibration of of pile-up compensation.
Cross-talk between channels.
Pedestal stability with time.
Aging.
Tª dependence.
ESD test on inputs and control pins.
Possible effects of pick-up noise cause by massive switching of digital
outputs (PCB dependent).
VI. Schedule.
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If no serious troubles are found systematic measurements might be
finished by end of January 2004.
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When should we ask to pass the PRR?
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If no defects are find and PRR is passed on February chip will be
ready for production in March?
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According to CMP it is possible “start production when you want”,
different from a MPW run.
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Sharing production masks with PS VFE chip might save some
money... It has been asked to CMP/AMS. Are the schedules for both
chips compatible?