Transcript CMOS VLSI Design

Introduction to
CMOS VLSI
Design
Lecture 5
CMOS Transistor Theory
Manoel E. de Lima
David Harris
Harvey Mudd College
Outline







Introduction
MOS Capacitor
nMOS I-V Characteristics
pMOS I-V Characteristics
Gate and Diffusion Capacitance
Pass Transistors
RC Delay Models
3: CMOS Transistor Theory
CMOS VLSI Design
Slide 2
Introduction
 So far, we have treated transistors as ideal switches
 An ON transistor passes a finite amount of current
– Depends on terminal voltages
– Derive current-voltage (I-V) relationships
 Transistor gate, source, drain all have capacitance
– I = C (DV/Dt) -> Dt = (C/I) DV
– Capacitance and current determine speed
 Also explore what a “degraded level” really means
3: CMOS Transistor Theory
CMOS VLSI Design
Slide 3
MOS Capacitor
 Gate and body form MOS capacitor
 Operating modes
– Accumulation
– Depletion
– Inversion
Vg < 0
+
-
polysilicon gate
silicon dioxide insulator
p-type body
(a)
0 < V g < Vt
+
-
depletion region
(b)
V g > Vt
+
-
inversion region
depletion region
(c)
3: CMOS Transistor Theory
CMOS VLSI Design
Slide 4
Terminal Voltages
Vg
 Mode of operation depends on Vg, Vd, Vs
+
+
– Vgs = Vg – Vs
Vgs
Vgd
– Vgd = Vg – Vd
Vs
Vd
– Vds = Vd – Vs = Vgd - Vgs
+
Vds
 Source and drain are symmetric diffusion terminals
– By convention, source is terminal at lower voltage
– Hence Vds  0
 nMOS body is grounded. First assume source is 0 too.
 Three regions of operation
– Cutoff
– Linear
– Saturation
3: CMOS Transistor Theory
CMOS VLSI Design
Slide 5
nMOS Cutoff
 No channel
 Ids = 0
 Vgs ≤ 0
Vgs = 0
+
-
g
+
-
s
d
n+
n+
Vgd
p-type body
b
3: CMOS Transistor Theory
CMOS VLSI Design
Slide 6
nMOS Linear
 Channel forms
 Current flows from d to s
V
– e from s to d
 Ids increases with Vds
 Similar to linear resistor
gs
> Vt
+
-
g
+
-
s
d
n+
n+
Vgd = Vgs
Vds = 0
p-type body
b
Vgs > Vt
+
-
g
s
+
d
n+
n+
Vgs > Vgd > Vt
Ids
0 < Vds < Vgs-Vt
p-type body
b
3: CMOS Transistor Theory
CMOS VLSI Design
Slide 7
I-V Characteristics
 In Linear region, Ids depends on
– How much charge is in the channel?
– How fast is the charge moving?
3: CMOS Transistor Theory
CMOS VLSI Design
Slide 8
Channel Charge
 MOS structure looks like parallel plate capacitor while
operating in inversion
– Gate – oxide – channel
gate
Vg
polysilicon
gate
W
tox
n+
L
n+
SiO2 gate oxide
(good insulator, ox = 3.9)
+
+
Cg Vgd drain
source Vgs
Vs
Vd
channel
+
n+
n+
Vds
p-type body
p-type body
3: CMOS Transistor Theory
CMOS VLSI Design
Slide 9
Channel Charge
 MOS structure looks like parallel plate capacitor
while operating in inversion
– Gate – oxide – channel
 Qchannel = CV
Cox = ox / tox
 C = Cg = oxWL/tox = CoxWL
 V = Vgc – Vt = (Vgs – Vds/2) – Vt
gate
Vg
polysilicon
gate
W
tox
n+
L
n+
SiO2 gate oxide
(good insulator, ox = 3.9)
+
+
Cg Vgd drain
source Vgs
Vs
Vd
channel
+
n+
n+
Vds
p-type body
p-type body
3: CMOS Transistor Theory
CMOS VLSI Design
Slide 10
Carrier velocity
 Charge is carried by e Carrier velocity v proportional to lateral E-field
between source and drain
 v=
3: CMOS Transistor Theory
CMOS VLSI Design
Slide 11
Carrier velocity
 Charge is carried by e Carrier velocity v proportional to lateral E-field
between source and drain
 v = mE
m called mobility
 E=
3: CMOS Transistor Theory
CMOS VLSI Design
Slide 12
Carrier velocity
 Charge is carried by e Carrier velocity v proportional to lateral E-field
between source and drain
 v = mE
m called mobility
 E = Vds/L
 Time for carrier to cross channel:
– t=
3: CMOS Transistor Theory
CMOS VLSI Design
Slide 13
Carrier velocity
 Charge is carried by e Carrier velocity v proportional to lateral E-field
between source and drain
 v = mE
m called mobility
 E = Vds/L
 Time for carrier to cross channel:
– t=L/v
3: CMOS Transistor Theory
CMOS VLSI Design
Slide 14
nMOS Linear I-V
 Now we know
– How much charge Qchannel is in the channel
– How much time t each carrier takes to cross
Qchannel
I ds 
t
W
 mCox
L
Cox= oxide capacitance
W
 = mCox
L
V  V  Vds V
 gs t
2  ds

V
  Vgs  Vt  ds Vds = β (Vgs-Vt )Vds -Vds2/2 = β (Vgs-Vt )Vds
2

It is a region called linear region. Here Ids varies linearly,
with Vgs and Vds when the quadratic term Vds2/2 is very small.
Vds << Vgs-Vt
3: CMOS Transistor Theory
CMOS VLSI Design
Slide 15
nMOS Saturation




Channel pinches off
Ids independent of Vds
We say current saturates
Similar to current source
Vgs > Vt
+
-
g
+
-
Vgd < Vt
d Ids
s
n+
n+
Vds > Vgs-Vt
p-type body
b
3: CMOS Transistor Theory
CMOS VLSI Design
Slide 16
nMOS Saturation I-V
 If Vgd < Vt, channel pinches off near drain
– When Vds > Vdsat = Vgs – Vt
 Now drain voltage no longer increases current
Qchannel
I ds 
t
W
 mCox
L
V  V  Vds V
 gs t
2  ds

V
  Vgs  Vt  ds Vds = β (V V )V -V 2/2
2
gs- t
ds
ds

Where 0 < Vgs – Vt <Vds, considering (Vgs-Vt )=Vds we have
Ids = β (Vgs-Vt ) 2/2
3: CMOS Transistor Theory
CMOS VLSI Design
Slide 17
nMOS I-V Summary
 nMOS Characteristics
3: CMOS Transistor Theory
CMOS VLSI Design
Slide 18
Example
 We will be using a 0.6 mm process for your project
– From AMI Semiconductor
– tox = 100 Å
2.5
V =5
2
– m = 350 cm /V*s
2
– Vt = 0.7 V
1.5
V =4
 Plot Ids vs. Vds
1
V =3
– Vgs = 0, 1, 2, 3, 4, 5
0.5
V =2
– Use W/L = 4/2 l
V =1
0
Ids (mA)
gs
gs
gs
gs
gs
0
 3.9  8.85  1014   W 
W
W
  mCox   350 

120
m A /V 2
 

8
L
L
 100  10
 L 
3: CMOS Transistor Theory
CMOS VLSI Design
1
2
3
4
5
Vds
Slide 19
pMOS I-V
 All dopings and voltages are inverted for pMOS
 Mobility mp is determined by holes
– Typically 2-3x lower than that of electrons mn
– 120 cm2/V*s in AMI 0.6 mm process
 Thus pMOS must be wider to provide same current
– In this class, assume mn / mp = 2
3: CMOS Transistor Theory
CMOS VLSI Design
Slide 20
Capacitance
 Any two conductors separated by an insulator have
capacitance
 Gate to channel capacitor is very important
– Creates channel charge necessary for operation
 Source and drain have capacitance to body
– Across reverse-biased diodes
– Called diffusion capacitance because it is
associated with source/drain diffusion
3: CMOS Transistor Theory
CMOS VLSI Design
Slide 21
Gate Capacitance
 Approximate channel as connected to source
 Cgs = oxWL/tox = CoxWL = CpermicronW
 Cpermicron is typically about 2 fF/mm
polysilicon
gate
W
tox
n+
L
n+
SiO2 gate oxide
(good insulator, ox = 3.90)
p-type body
3: CMOS Transistor Theory
CMOS VLSI Design
Slide 22
Diffusion Capacitance
 Csb, Cdb
 Undesirable, called parasitic capacitance
 Capacitance depends on area and perimeter
– Use small diffusion nodes
– Varies with process
3: CMOS Transistor Theory
CMOS VLSI Design
Slide 23
Pass Transistors
 We have assumed source is grounded
 What if source > 0?
VDD
– e.g. pass transistor passing VDD
VDD
3: CMOS Transistor Theory
CMOS VLSI Design
Slide 24
Pass Transistors
 We have assumed source is grounded
 What if source > 0?
VDD
– e.g. pass transistor passing VDD
VDD
 Vg = VDD
– If Vs > VDD-Vt, Vgs < Vt
– Hence transistor would turn itself off
 nMOS pass transistors pull no higher than VDD-Vtn
– Called a degraded “1”
– Approach degraded value slowly (low Ids)
 pMOS pass transistors pull no lower than Vtp
3: CMOS Transistor Theory
CMOS VLSI Design
Slide 25
Pass Transistor
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
3: CMOS Transistor Theory
CMOS VLSI Design
Slide 26
Pass Transistor Ckts
VDD
VDD
VDD
VDD
VDD
VDD
Vs = VDD-Vtn
Vs = |Vtp|
VDD-Vtn VDD-Vtn
VDD
VDD-Vtn
VDD-Vtn
VDD
VDD-2Vtn
VSS
3: CMOS Transistor Theory
CMOS VLSI Design
Slide 27
Effective Resistance
 Shockley models have limited value
– Not accurate enough for modern transistors
– Too complicated for much hand analysis
 Simplification: treat transistor as resistor
– Replace Ids(Vds, Vgs) with effective resistance R
• Ids = Vds/R
– R averaged across switching of digital gate
 Too inaccurate to predict current at any given time
– But good enough to predict RC delay
3: CMOS Transistor Theory
CMOS VLSI Design
Slide 28
RC Delay Model
 Use equivalent circuits for MOS transistors
– Ideal switch + capacitance and ON resistance
– Unit nMOS has resistance R, capacitance C
– Unit pMOS has resistance 2R, capacitance C
 Capacitance proportional to width
 Resistance inversely proportional to width
d
g
d
k
s
s
kC
R/k
2R/k
g
g
kC
kC
s
3: CMOS Transistor Theory
kC
d
k
s
kC
g
kC
d
CMOS VLSI Design
Slide 29
RC Values
 Capacitance
– C = Cg = Cs = Cd = 2 fF/mm of gate width
– Values similar across many processes
 Resistance
– R  6 KW*mm in 0.6um process
– Improves with shorter channel lengths
 Unit transistors
– May refer to minimum contacted device (4/2 l)
– Or maybe 1 mm wide device
– Doesn’t matter as long as you are consistent
3: CMOS Transistor Theory
CMOS VLSI Design
Slide 30
Inverter Delay Estimate
 Estimate the delay of a fanout-of-1 inverter
R in pMOS is divided by 2 since its width is the double of the nMOS
A
2 Y
2
1
1
3: CMOS Transistor Theory
CMOS VLSI Design
Slide 31
Inverter Delay Estimate
 Estimate the delay of a fanout-of-1 inverter
2C
R
A
2 Y
2
1
1
2C
2C
Y
R
C
C
C
3: CMOS Transistor Theory
CMOS VLSI Design
Slide 32
Inverter Delay Estimate
 Estimate the delay of a fanout-of-1 inverter
2C
R
A
2 Y
2
1
1
2C
2C
2C
2C
Y
R
C
R
C
C
C
C
3: CMOS Transistor Theory
CMOS VLSI Design
Slide 33
Inverter Delay Estimate
 Estimate the delay of a fanout-of-1 inverter
2C
R
A
2 Y
2
1
1
2C
2C
2C
2C
Y
R
C
R
C
C
C
C
d = 6RC
3: CMOS Transistor Theory
CMOS VLSI Design
Slide 34
+5V
+5V
R
In
Vil=0
Roff  1010
X
Out
Iih
Ioh
Voh(min)
Vih(min)
GND
GND
Transistor não conduz
Capacitor
Tensão(V)
Vih(min)
Nível ´1´
Tempo (seg)
CMOS VLSI Design
+5V
+5V
R
In
Vih=´1´
Vol(max)
Ron  1 KW
Out
Iil
Iol
Vil(max)
GND
GND
Transistor conduz
Capacitor inicialmente carregado = “1”
Tensão(V)
Nível ´0´
Vil(max)
Tempo (seg)
CMOS VLSI Design