Transcript A CMOS compatible PolyFuse element used in a One - Mos-AK

PolyFuse OTP Cell
A CMOS compatible PolyFuse element
used in an One Time Programmable circuit
Johannes Fellner
austriamicrosystems AG
08.04.2005
A leap ahead in mixed signal
Purpose
Design an OTP Element in a Standard 0.35um CMOS Process
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PolyFuse element defined
Programming within process specification
High lifetime & reliability
Implementation of the OTP Element into an IP-Block
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Infield programming option
High programming yield
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Outlook
3
Introduction into PolyFuse OTP
Programming Characteristics
Cross Sections
Reliability and Yield
WAT Implementation
Design Issues for IP Block
Summary
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Introduction
PolyFuse used as an OTP base element
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Poly Silicon with Tungsten Silizide
Low ohmic standard resistance (<100W)
High ohmic after programming (>10kW)
Contact
Barrier
Poly Silicon
4
Tungsten Silicide
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Contacts
PolyFuse Element
Programming Features
Poly Fuse
Area
A
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Programming in standard CMOS
process
5
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Current programming
Infield programming possible
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Tungsten Plug (Contact)
Tungsten Silicide
Poly Silicon
Programming Characteristic
Imax
Imelt
Ilinear
tprog 0µs
Iheat: Temp. is raising
Imelt: Tungsten Silicide is melting
Imin Ialloy
Iheat
Vprog
V
Ilinear: Linear resistor characteristics
Imax: Maximum current of
minimum resistance
Iosc
1µs
2µs
3µs
Imin: Local current min.
Iosc: Oscillation because of break
Ialloy: No autonomous current
pinch off
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Iprog
mA
Cross Section
Typical Current Programmed Poly Fuse
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Active PolyFuse region no longer has
Tungsten included
High ohmic stable alloy
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Minimal lifetime drift
of the resistance value
Field Oxide
Tungsten Plug
Tungsten Silicide
Poly Silicon
Poly Silicon
approx. 40nm
Field Oxide
Substrate
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Local break of a few nm
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Cross Section
Low Current Programmed Poly Fuse
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Inhomogenious temperature gradient
during programming
Tungsten Plug
Low ohmic resistor
Lifetime drift to higher
resistor values
Field Oxide
Tungsten Silicide
Tungsten Silicide
Poly Silicon
Poly Silicon
Field Oxide
Substrate
Substrate
8
Tungsten Plug
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Cross Section
Low Current Programmed Poly Fuse
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High energy is forcing the Tungsten
seperation
Break before Tungsten completely
removed
Tungsten Plug
Tungsten
HALO
Relatively high ohmic resistor
Lifetime drift to lower resistor
values possible
Field Oxide
Tungsten Silicide
Tungsten Silicide
Poly Silicon
Tungsten
Poly Silicon
Field Oxide
Substrate
Substrate
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Tungsten Plug
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Reliability Investigations
Lifetime Drift over Time
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2000h BurnIn@125 °C
HTOL Test JESD22-108
Lifetime Drift Investigated for
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typical current programmed PolyFuses
low current programmed PolyFuses
high current programmed PolyFuses
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Yield Analysis
Testchip with Geometrical Variations
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Variation of size of programming transistor
Variation of PolyFuse length and width
Design Of Experiment (DOE) Run
With of Stack: Tungsten Silicide - Poly Silicon
Tungsten Silicide thickness variation
Poly Silicon thickness variation
Analysis
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Programming within specified limits
Variable temperature and supply specifications
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Process Control
WAT Structure
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PolyFuse Element
Burning NMOS Transistor
Measurements
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Resistor of unprogrammed PolyFuse
Resistor of programmed PolyFuse
Current of Burning Transistor
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Design Issues
IP Blocks with PolyFuses Designed
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32 bit
128bit
Optimized Programming Path
PolyFuse
Related programming transistor
Special Test Function
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to guarantee lifetime stability
for infield programming
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Design Requirement
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A programmed PolyFuse resistance must be
larger than 10kW after programming
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The resistance of a programmed PolyFuse is
checked at 1kW during lifetime operation
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This margin ensures proper operation of
programmed PolyFuses over lifetime
Requirement for Infield Programming
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14
Testmode to measure the unprogrammed
PolyFuse resistance (<100W)
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Requirements For Lifetime Stability
Base Cell
Supply
Principle Schematic
Poly
Fuse
PolyFuse Element
Programming Transistor
Current Mirror
NMOS
Control
Voltage
Testmodes
Level
Detector
Different
Bias Currents
Programming Part
15
Current
Mirror
Reading Part
Digital
Level
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Base Cell
Principle Layout
LOGIC
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PROM Storage
RAM Access
LOADing Mode
PROGramming Mode
Optional Parallel Out
PROG LOAD
PROM
RAM
WRITE
READ
Parallel
Out
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OTP Block
Parallel Dataout: Bits m0 – (m-1)7
- 32bit and 128bit Version
- 32bit Parallel Out
- Address Decoder
- Autoloader at Startup
- Combination up to 2kbit
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AD
Address DRE
SS
BUS
Enable
Mode
BUS
de
co
der
Mode
m7
m0 m1 m2 m3
Base Cells
30
20
10
00
31
21
11
01
32
22
12
02
33
23
13
03
Base
Line
37
27
17
07
DATA Transfer
Parallel Dataout: Bits 00 – 17
8bit
DATA
BUS
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Principle Layout of OTP Block
Conclusion
- Reliable Programming Conditions
- Programmable over whole Process Range
- Lifetime Stability
- Process Control
- Infield Programming Option
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- High Programming Yield