Transcript 09_Cyclone

‫خانواده هاي ‪FPLD‬‬
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Cyclone FPGA
• SRAM-based
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Altera Cyclone Devices
Cyclone
FPGA
Cyclone II
FPGA
Cyclone III Cyclone IV Cyclone V
FPGA
FPGA
FPGA
Year
introduced
2002
2004
2007
2009
2011
Process
technology
130 nm
90 nm
65 nm
60 nm
28 nm
Recommen
ded for new
designs
Yes
Yes
Yes
Yes
Yes
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Gigabit Transceiver Blocks
Cyclone V Architecture
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Cyclone V Architecture
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LAB Structure
• LAB:
– 10 ALMs
• Logic implementation
– Local interconnect:
• Fast connection between ALMs
• MLAB (Memory LAB):
– Can be configured as 32x2 dual port SRAM.
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‫‪ALM Structure‬‬
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‫‪Cyclone V‬‬
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Cyclone V Characteristics
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On-Chip Memory
1. MLAB Blocks:
– Wide and shallow
– 640-bit blocks
– 10 ALMs:
•
Each 32 x 2 bit blocks
– Configured as shift registers and FIFO.
2. M10K Blocks:
– 10 Kb blocks
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Memory Resources
• One type of chips
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Memory Resources
• Configurations in single/dual-port modes
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M10K Port Modes
• Single-Port:
– Only one read or one write operation at a
time
• Simple Dual-Port:
– Can simultaneously perform one read and
one write operations to different locations
• True Dual-Port:
– Can perform any combination of two port
operations:
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• Two reads, two writes, or one read and one write
at two different clock frequencies.
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Computational Blocks
• DSP Blocks:
– Multiplication
• 27 x 27
• 18 x 18
• 9x9
– Add/subtract, accumulation
• Efficient calculation of
Σ xi . yi
– Constant storage:
• No need to input from external ports in run-time
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‫‪DSP Block‬‬
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FIR (Finite Impulse Response) Filter
y[n] = C0.x[n] + C1.x[n-1] + … + CN.x[n-N]
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‫‪Cyclone V‬‬
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Inferring Multipliers
• In Quartus II:
• Use attribute syn_multstyle:
– lpm_mult:
• Multipliers implemented in DSP blocks
– logic:
• Multipliers implemented as LEs
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Inferring Multipliers
architecture beh of onereg is
signal temp : std_logic_vector (15 downto 0);
attribute syn_multstyle : string;
attribute syn_multstyle of temp : signal is
"logic";
begin
temp <= a * b;
r <= temp when en='1' else c;
end beh;
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Inferring Multipliers
• In XST:
• Use attribute mult_style:
– auto: (default)
• XST looks for the best implementation
– block:
• Multipliers implemented as DSP block
– lut:
• Multipliers implemented as LUTs
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Inferring Multipliers
architecture beh of onereg is
signal temp : std_logic_vector (15 downto 0);
attribute mult_style: string;
attribute mult_style of temp : {signal|entity }
is "{auto|block|lut|pipe_lut}";
begin
temp <= a * b;
…
end beh;
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Hard Processor Core
• Some chips: Arm Cortex-9
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– Single- or dual-core processor with up to 925
MHz maximum frequency
– Hardened embedded peripherals
– Hardened protocol PCIe
– Hardened multiport memory controller, shared
by the processor and FPGA logic, supports
DDR2, DDR3, and LPDDR2 devices
– Level-1 cache: 32 KB
– Level-2 cache: 512 KB
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IO Element
Device
Variableprecision DSP
blocks
Fractional
PLLs
Maximum user
I/Os
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5CGXC3
51
5CGXC4
70
5CGXC5
150
5CGXC7
156
5CGXC9
342
4
6
6
7
8
208
336
336
480
560
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IO Element - OCT
• OCT (on-chip termination):
– For impedance matching
– Resistor value can be programmed
– No need for on-board termination
•  Large space saving
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IO Element – Open-Drain Outpout
• Open-drain output:
– Can produce hi-Z output
– Needs a pull-up resistor to generate logic ‘1’
• Programmable pull-up resistor avoids on-board
pull-up
– Open-drain outputs can be used for wired
AND
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IO-Element – Slew Rate
• Slew rate:
– Maximum rate of change of output voltage per
unit of time (V/sec)
– Max (dvout(t)/dt)
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IO-Element – Slew Rate
• Slew rate:
– Designer can choose fast or slow rate
• Fast: for systems with high performance systems
• Slow: for reliability in systems faced with high
noise
– At the cost of speed
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Clock Management
• Fractional PLLs:
– To avoid multiple oscillators
– Programmable frequencies
– Jitter/skew removal
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Transceiver Blocks
• 3 to 12 blocks
• 3.125 to 6.144 Gbps
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Embedded Processor
• In some chips, hard processor core:
– Arm Cortex-A9
• Single core, dual core
• Up to 1.5 GHz
• 3750 MIPS
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Configuration
• When powered up:
– Reads configuration bitstream from
•
•
•
•
An Altera-compatible EPROM
A standard EPROM
A RAM in a computer system
An intelligent processor or controller
• Configuration time:
– 10 to 50 ms
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‫‪Altera Stratix‬‬
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Stratix Chips
• LUT-based FPGA
• Logic block structure, interconnection
architecture, memory blocks IO blocks,
Transceiver blocks:
– Very similar to Cyclone
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‫‪Altera FPGAs‬‬
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Stratix vs. Cyclone
Stratix Family
Higher bandwidth
Higher logic density
Cyclone Family
Lower cost
Lower power
consumption
Higher performance
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‫‪Stratix V‬‬
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