Transcript 07_3_synthesis_power_timing

Power Optimization
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Power optimization
• Transitions cause power consumption.
• Logic network design helps control
power consumption:
– minimizing capacitance;
– eliminating unnecessary glitches.
Pdyn=
∑a.f.CL.Vdd2
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Power estimation tools
• Power estimator approximates power
consumption from:
– Netlist;
– Primary input transition probabilities;
– Capacitive loading.
• Two Types:
– Switch/logic simulation-based
– Statistical models
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Power optimization
• Leakage in more advanced processes.
– Even when logic is idle.
– Solution:
• Reducing junction temperature by using fans,
heat sinks, or design modifications
• Reducing voltage levels of the IOs.
– Each bank requires a separate power supply.
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Power optimization
– Maximizing the number of unused and
unpowered banks.
– Clock gating:
• Clocks that drive logic, embedded memory,
SerDes, and other FPGA primitives can be
disabled when their operation is not required.
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Glitching example
• Gate network:
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Adder Chain Glitching
d
a+b+c+d
c+d
c
a+b+c
a+b+c
a+b
a+b
a+b
good
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bad
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Factorization for low power
• Proper factorization reduces glitching.
• ‘a’ has high transition probability, ‘b’ and ‘c’ low probabilities
f(a, b, c)
bad
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f(a, b, c)
good
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Factorization techniques
• Reduce number of logic levels through
which high-probability signals must
travel
–  Reduce propagation of glitches.
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Example (ALU)
• ALU output is not used for every cycle
–  If ALU inputs change, the energy is
needlessly consumed
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Example (ALU)
• Control Signal selects whether data is allowed
to pass the logic or the previous value is held to
avoid transitions.
Data
Logic
D
Q
Control
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Low Power Design Techniques
• Reduce wiring capacitance
– Get post-layout feedback for better
capacitance estimations
• Place and route to minimize capacitance
of nodes with high glitching activity.
• Reducing FPGA operating voltages.
• Reducing operating frequencies.
• Reducing the overall toggle rate of the
design.
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Low Power Techniques
• FPGA Selection:
– Spartan6 and Virtex-6 -1L speed grade
option for low-power applications
• Requires lower core voltage.
– FPGAs with smaller die size and lower pin
count consume less power.
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Low Power Techniques
• Synthesis Options:
– XST, MAP and PAR “-power” option
reduces dynamic power consumption.
– Quartus-II has Power-Driven Synthesis and
Fitter
• Disabling unused functional blocks:
– By deasserting enable inputs to modules that
use Xilinx BRAMs when not accessed.
• RAMs, ROMs, and FIFOs,
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State assignment
• One-hot:
– usually a good choice for optimizing speed or
reducing power.
• Gray:
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– appropriate for controllers exhibiting long
paths without branching.
– Minimizes hazards and glitches.
– Gives good results when implementing the
State Register with T Flip-Flops.
– Can be used to minimize power
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State assignment
• Compact:
– Minimizes the number of bits in the state
register.
– Minimizes next state equations.
• Speed1
– oriented for speed optimization.
– The number of bits for a State Register
depends on the specific FSM
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Another Sample Report
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• Changed to gray automatically
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