Transcript Session 5.1 - Board Test Workshop Home Page

We buy good boards!
(Improve yield from design to production)
Christophe LOTZ
[email protected]
ASTER Technologies
IEEE 8th International
Board Test Workshop
Content
•
•
•
•
•
•
Introduction
Yield improvements
Defect prevention vs. Defect detection
Test Coverage vs. Test Efficiency
Production model
Technologies convergence
• Coverage Analysis
• + Traceability & Quality tools
• = Test Innovation
•
Conclusion
2
The world changes
•
Electronic design and production changes:
 Functional complexity of electronic boards.
 Staggering board density.
 Outsourcing of board production.
Non-functional channels
SMD, fine pitch,
BGA, buried via
Block 3
Block 1
Block 2
We buy good boards
3
Yield improvements
Defect Prevention
Defect Detection
•
•
•
For a lot of people, Quality is costly. However,
Non-Quality can be fatal.
When it is impossible to reduce the task, it is
always possible to reuse the results for other
purpose: i.e. Test for Designability, Production
line optimization, Repair Cycle, Product life…
Combine Design Re-Use with Test Re-Use…
4
Defect prevention
•
Design Flow
•
•
•
•
•
Electrical DfT rules checking from schematic.
Probe optimization from schematic.
Probe placement – Mechanical DfT rules.
DfM – Design for Manufacturing.
Coverage estimation
–Inspection: AOI, AXI
–Structural test: ICT,FPT,MDA,BST
–Functional test: In-System test, Emulation…
• Lack of automation/understanding between design
and production center (The WALL)!
5
Defect Prevention
•
Manufacturing flow
• Assembly machine
–Feeder control/supply chain management,
–Passive measurement during placement.
• Traceability tools
–Work In Process,
Quality System must
–Box Building.
be able to report
• Repair station
the amount of defects
by partnumber
–CAD data,
–Fault ticket,
–Diagnosis.
–Defect occurrence/re-occurrence
6
Defect Detection
Solder
X-Ray
•
•
•
•
•
In-Circuit
(unpowered)
Insufficient
Excess
Cold Solder
Marginal
Joints
Voids
•
•
•
•
•
• Extra Part
• Bridging
• Tombstone
• Misaligned
Material
Polarity (PCAP)
•
•
•
Missing
Gross Shorts
Lifted Leads
Bent Leads
• Polarity
AOI
(unpowered)
•
•
Dead Part
Bad Part
In-System
Programming
Functionally Bad
Short/Open on PCB
• Shorts
• Open
JTAG
• Inverted
memory
• Wrong Part • At-speed
tests
• At-speed
interconnect
• Fault Insertion
• Gate level
diagnosis
Placement
7
Defect Detection
MPS
PPVS
PCOLA/SOQ
PCOLA/SOQ/FAIM
Material
Value
Correct
Correct
Live
Live
Correct
Correct
Live
Live
Polarity
Orientation
Orientation
Solder
Short
Short
Open
Open
Quality
Quality
Placement
Solder
Function
Presence
Function
Feature
At-Speed
In Parallel
Measurements
8
Defect Detection
•
•
One coin/two sides: Defect  Coverage
Drill-down on flows for more defect categories
MPS, PTC, PPVS,
PCOLA/SOQ
PCOLA/SOQ/FAIM…
Design
Manufacture
Function
Buy Materials
(Supply chain)
Place
components
Soldering
Presence
Orientation
9
Test Coverage
•
Demonstration using an absurd example
• Board - 4 components: 3 resistors, 1 BGA.
• The 3 resistors are measured with very high
accuracy.
• No test on the BGA.
• Is the board test score really 75%?
3 resistors / 4 components
• We need something to weight the coverage… It
must be credible, easy to update to reflect growing
electronics complexity.
10
Test Efficiency
•
For each category (MPS) of defects (D), we
associate the corresponding coverage (C).
 DM  CM +  DP  CP +  DS  CS
Effectiveness =
•
 DM +  DP +  DS
The test efficiency is based on a coverage
balanced by the defects opportunities.
Df
Cf
We need a better coverage
where there are
more defect opportunities!
11
Test Efficiency
•
Coverage
• Material=0%, Placement=100%, Solder=100%
•
Massive production:
• Material=2PPM, Placement=10PPM,
Solder=10PPM
Everything
• Test efficiency=90.9%
is relative.
•
High mix:
• Material=15PPM, Placement=10PPM,
Solder=15PPM
• Test efficiency=60.5%
12
Defect universe
•
How to know your defect universe?
• Average number: It is better than nothing as it
make possible to differentiate a resistor from an IC.
–www.ppm-monitoring.com
–www.inemi.org
• DPMO collected from the real production line
–Placement defects and
soldering defects DPMO
by package.
Escape rate
–Material defects
by partnumber.
IPC
13
Production model
•
Summarize the coverage in a limited set of
numbers that will guide the test strategy choice.
Good
Products
shipped
First Pass
Yield
Yield
Pass
Escape
Fail
False
reject
Test
Bad
Good
Products
repaired
Fall-Off
Rate
Bad
•
The “Escape” is an effective way to measure
the manufacturing quality.
14
Technologies convergence
•
•
•
Design re-use is widely accepted throughout
the electronics industry.
Design | test specification | test development |
quality management are isolated in separated
silos. Limited data exchange between silos.
It is time for test-reuse and technologies
convergence.
• It increases the test value.
• It decreases the test cost.
15
Functional test
•
Functional coverage could be managed as
described in BTW06 paper.
• By Declaration
Schematic and layout
viewers used to simplify
coverage declaration.
16
Functional test
• By Inheritance
Recognition
of pre-analyzed modules
with corresponding coverage
Derivation and accumulation
for the new design.
17
Functional test
•
For a complex board, it represents 3 to 5 days
work to analyze the functional coverage if
nothing has been prepared from design flow.
•
Benefits:
• Get the overall coverage
(inspection + structural + functional),
• Identify overlapping (potential optimization),
• Identify lack of coverage (Failure Mode and Effects
Analysis).
Tested?
18
Test Innovation
•
Functional test
• Functional Test coverage tool used as functional
test specification tool.
–Define test strategy early in the design flow.
–Identify unique test contribution.
–Avoid un-required overlapping.
• Functional Blocks recognition make possible to
develop an Automatic Functional Test Generator.
–Automate test development and coverage
analysis in high-hierarchical design flow.
–Integrate Designer knowledge for repair
purpose.
19
Test Innovation
•
Test line
• Test coverage results re-used in functional test
repair station.
–The Pass tests tell us which defects are not on
the board.
–The Fail tests tell us which defects could be on
the board.
• Combined with historical data in order to guide
diagnosis to the most probable source of defect.
Repair
Tester interface
Parsing /
Recording
Viewer
/ Advisor
Database
Traceability
Coverage
Database
Quality
Testers
Data processing
/ Exploitation
CAD
Data
20
Test Innovation
•
•
Dynamic test program optimization driven by
Quality management tool.
When the test is the bottleneck of the
production:
• The Quality Management system is collecting
DMPO in real time.
• Defect profile is used to tune the assembly line.
• According to the defect profile, the test program is
dynamically optimized.
No need to maintain
test on defect that
no longer occurs !
21
Conclusion
•
•
•
From design, during production and in a more
general way, through the whole product life
cycle, coverage estimation permits the test
process to be optimized.
By deploying various testers in the best order,
at the best time, with controlled levels of
redundancy, costs can be reduced and quality
levels raised.
The economic challenges are critical: the tools
to meet them are available.
22