Transcript Document
The PCI Test Stand Tom Junk, Catalin Ciobanu University of Illinois Project Update and test-stand description Many thanks to: Sergio Zimmerman, Guilherme Cardoso, Brad Hall, Greg Deuerling, David Slimmer for the PTA and PMC cards Todd Moore, Mike Kasten, Allison Sibert, Mike Haney at UIUC for FPGA development tools and interface cards Lorenzo Uplegger (BTeV) -- PTA firmware The Hardware P C I Ribbon cables with Samtec Connectors PTA Power Supplies PMC Adapter Board B u s Chip Test Board Hybrid test Board Connectors for Guilherme’s MPC adapter board PTA: PCI interface. 2Mb memory (2 banks of 1 Mb each). Altera FPGA. Connector to PMC. PMC: Xilinx FPGA with flexible I/O standards. Single-ended or differential, I, O, or bidirectional. On-chip memory for sequencing complicated patterns. Latches data and packs it for storage in PTA RAM. Firmware PTA Firmware Courtesy of Lorenzo Uplegger, Milano • Controls memory access -- allows PMC to write to one memory bank while PCI bus reads the other bank. Also allows automatic switchover for writing when one bank fills. • Forwards control/data signals to PMC PMC Firmware T. Junk, University of Illinois • Control and data lines for single chip and hybrid. 2.5V single-ended, LVDS, and bidirectional LVDS. • 16 Registers for control of operation • Direct writing to output lines • Direct readback of input lines continued.. PMC Firmware -- cont’d PMC registers • Controls writing to PMC pattern memory 16 K words. Similar function to LBL pattern boards. • Readback of PMC pattern memory • Control of sequence execution address, start/stop. 50 MHz pattern sequencing. • Selection of sequence or register output to control lines • Selection of which input lines to read back: MPC or chip/hybrid lines. (New!) • Control of VCAL DAC (8 bits) (New!) New DAC feature -- resistor network being added to the adapter card, using 8 single-ended 2.5 V signal lines on one of the Samtec connectors. Provides low-current programmable voltage up to 2.5 Volts. Adapter board still being wired up. Needed for gain measurement. To Do list for Hardware/Firmware • Finish wiring up adapter board with DAC resistor chain. Test it with single-chip board. Software task: write a gain calibration scan. • Test MPC interface (at FNAL) • Old plan -- double the outputs for multiple burnins. Now the four Samtec connectors on the PMC are used for: A and B: Chip board and hybrid test, DAC control C and D: Access to Guilherme’s MPC adapter Needed this arrangement to test firmware with a single chip to make sure new I/O additions did not break the functionality. Passed test! Can arrange for two MPC adapters in the future. Status of Old Report of “Odd things” • PTA -- more clocks than data words needed to get data through pipeline. We use OBDV as a clock because anything else may be out of time. Workaround -- read twice and discard the last one. Works fine! First read after initialization is different however (missing first two words -- chipid+cellid+first channel) • OBDV needed a 100 Ohm resistor for the hybrid -- problem understood -- updated initialization string -- now only one chip at a time talks. Resistor no longer needed. • Delays in Xilinx FPGA still very important. Discovery that keeping memory blocks physically close together on the FPGA (close to address computation and output latching) improves reliability. Found the right constraints. • A previously unreported odd thing: Last four channels and first channel calibration mask bits do not function properly for the chip we got. Project Plans • Test with MPC and stave • Finish implementing VCAL gain scan • Design more permanent adapter boards -not wire-wrapped but printed circuits. Design to test hybrids, MPC interface. JPC? Others? How are single hybrids tested during production? • Use for burnin?