Transcript Document

Parallel JPEG2000
Compression System
Performed by: Dmitry Sezganov, Vitaly Spector
Instructor: Stas Lapchev, Artyom Borzin
Abstract

High data rate due to rapid growth in imaging capacity.

Typical image data rates are several Gbits per second.

Solution – image compression.

Compression must be done prior to storage.

High compression ratio and performance is required.

Suitable compression algorithm should be used.
Abstract
JPEG2000
Encoder
JPEG2000
Decoder
JPEG vs. MPEG vs. JPEG2000
JPEG
MPEG2/4
-
JPEG2000
Still images
Yes
No
Yes
Large images
No
No
Yes
Lossless compression
Lossy compression
Error resilience
We choose JPEG2000 algorithm.
Comparison
Compression Rate: 130:1
Wavelet (7KB, 5922 bytes)
JPEG2000
JPEG (7KB, 6220 bytes)
ADV202 Overview
Features of ADV202:
Single-Chip JPEG2000 Compression/Decompression cheap
Solution.


Programmable Tile/Image Size.
Flexible pixel interface supporting 8, 10, 12, 14, 16-bit Y, Cr,
Cb pixels.


Supports various interfaces (also DMA).
Satellite imagery
2.5km=5000pix
Pixel=1/4 m²
8.5km/s
1m
1m
2.5km
m
pix
8500[ ]  5000[ pix]  2[
] 12[bits]
s
m
 1Gbps
Requirements & Environment
Project requirements:

Building multi-unit compression prototype system.

Easy extension.

Input bit rate is 1.2Gbps.

Fast HW implementation.
Environment:

Virtex-II Pro Development Board
 ADV202

PC
JPEG2000 Video Codec
Image tiling
5000
Input:

Data arrives line by line.
Input bit-rate 1.2Gbps  2
ADV202 devices.

5000 pixels width  2500 to
each ADV202.
Tile#0
Tile#1
4096

Output:

Synchronization needed.
Coded stream is taken by
pieces from each ADV202,
strongly in order.

2500
Tile#2
Tile#3
Architecture
Coded stream
Compression
Unit
Channel #2
Testing Unit
1.2 Gbps
Generator
Channel #1
Raw stream
Coded stream
and controls

Testing Unit – simulates high bit rate camera.

Channel#1 – Ethernet; Channel#2 – Rocket IO;

Initialize the Generator with a picture.

The Generator sends the picture periodically.
Testing Unit
Generator
Compression Unit
PC
Logic
Logic
Architecture
Loading image
through Ethernet
Memory
Duplicating and sending
image through Rocket
I/O channel
Tiled image data
Codec
PCB
Bus
Data flow
Commands
GUI interfaces our system through the following command:

Reset.

Read/Write ADV202 register.

Read/Write Codec Controller register.

Start TX.

Stop TX.

Resume TX.

Statistic commands.
Network Topology
Each command – packet.
 Packet ID defines packet’s source and destination.

PowerPC2
PowerPC1
Controller
Load image (data for compression).
 Command to PPC1 (from PC to PPC1).
 Command to PPC2 (from PC to PPC2).
 PPC1 to Controller (duplicated image stream).
 Controller to PC (coded data).
 PPC2 to PC (debug, statistics info).

Software

PPC runs web server
Has IP address, standard
capabilities like answering pings.

Windows socket
programming for Ethernet.


MFC – writing GUI.
Can be reached from any
computer on the local network.

When PPC accepts connection from PC – full duplex
conversation.

Testing Board Design
ISBRAM
16
DCR Bus
64
PPC405
Processor
Block
16
PLB
BRAM
Packet
Processing
Engine
I/F Logic
16
SDRAM
Controller
PLB
BRAM
Controller
PLB
PLB
Arbiter
PLB2OPB
Bridge
Ethernet
Controller
To PC
OPB
OPB
Arbiter
LCD
Controller
Rocket I/O
Transceiver
GPIO
Controller
UART
LITE
TX
RX
Compression Board Design
16
ISBRAM
64
PPC405
Processor
Block
Packet
Processing
Engine
I/F Logic
16
Rocket I/O
Transceiver
DCR Bus
Codec
Controller
Module
Interrupt
Controller
16
PLB
PLB
Arbiter
PLB2OPB
Bridge
PLB
BRAM
OPB
OPB
Arbiter
LCD
Controller
GPIO
Controller
UART
LITE
PLB
BRAM
Controller
TX
RX
To Codecs
Codec Controller Design
Interrupt
Controller
Rocket
IO
Interface
64 bit PLB Bus
Bus Interconnect Logic
M
o
d
e
CPU
R
e
s
e
t
32
Rocket IO Packet Processing Module
36
36
DCR
B
l
o
c
k
FIFO
In
B
l
o
c
k
FIFO
Out
Soft RESET
36
36
Multiplexing
Logic
Multiplexing
Logic
ispGDX240AV Crosspoint Device
ADV202
PCB
ADV202
Our logic.
Hard
RESET
Hardcore.
Softcore.
Extension and Scalability
Interrupt
Controller
Rocket
IO
Interface
64 bit PLB Bus
Minimal extension
by 2500 pixels.

Bus Interconnect Logic
CPU
R
e
s
e
t
32
M
o
d
e
Rocket IO Packet Processing Module
36
36
DCR
B
l
o
c
k
FIFO
In
B
l
o
c
k
FIFO
Out
Soft RESET
36
36
Multiplexing
Logic
Multiplexing
Logic
ispGDX240AV Crosspoint Device
ADV202
PCB
Faster channel
needed.

ADV202
Recommended
extension by 5000.

Hard
RESET
RIO Processing Module
Bus Core Interconnect Logic
Local Bus
StartRD
Packet
Requesting
Generator
StartTX
Packet
Retrieving
Controller
Grant_1
Packet
Sending
Controller
Grant_2
RioRDY
Grant_3
Grant_0
FIFO_in
FIFO_out

Round-robin arbitration.

Priority on transaction duration by predefined settings.

Clock frequency is 1/2 of PLB clock.
Packet
Starting TX
Codec Controller - FIFO

FIFO Write interface
FIFO Write interface
36
36
36
36
36
36
FIFO1
512X36
FIFO2
512X36
FIFO3
512X36
FIFO4
512X36
36
36
36
36
36
36
JP1
FIFO_in
JP2
FIFO_in
36
36
36
36
FIFO Read interface
FIFO Read interface
Each FIFO block = 1 BRAM(18Kbit).

9KBytes per ADV202.

Different clocks on both sides.
clock_in
fifo_gsr_in
write_en_in
read_en_in
write_data_in
4
fifostatus_out
36
full_out
empty_out
read_clock_in
read_data_out
FIFO
512X36
36
PCB Design Considerations
Codec PCB is a daughter card - P160 connector must be
mounted.


2 ADV202 units to sustain required data rate.

2 X 76 ADV signals vs. only 109 P160 available pins.
 Apply
Switching Logic to achieve max flexibility.
PCB must meet 3 tests requirements ( SEU, Latch Up, Total
Dose ) .

 Appropriate
connection to signals must be
implemented for debug purposes - Mictor.
Switching Logic Requirements
Multiple interfaces and Operation modes – Signal switching
( static Signal rerouting )


Bi directional signals – signal direction switching ( dynamic )
 ADV202
Share signals – 1 to 2 signal routing .
Single ADV202 clock – combinatorial logic, uniform signal
propagation.

Some signals are not routed through the switching logic
( clocks, essential signals )


Fixed High or Low Output.
106 P160 + 62 X 2 ADV202 signals – minimum 230
switching logic I/O pins

ispGDX240 Overview
240 I/O, “Any Input to Any Output”
Routing

Fixed HIGH or LOW Output Option
for Jumper/DIP Switch Emulation


4.5ns Input-to-Output delay

3.3V Core Power Supply

240 I/O pins
Signal Routing
P160
49
46
62
60
ispGDX240VA
V
i
r
t
e
x 60
3
ADV202
VClk, Mclk, Rst
62
ADV202
Orcad
PCB Features

Devices: 2 ADV202, ispGDX240, Voltage Monitor.

Connectors: P160 ( JX1 & JX2 ), ispGDX JTAG port.

Header: external power supply and Reset.

Debug capabilities:
 4 Mictor connectors ( 32 signals each ) – Logic Analyzer.
 Power supply voltage LED indicators.
 Reset push button.
 Test points: Ground and Vcc.
 Pads for clock probing.
Tests Requirements

The 3 tests are:
 SEU – full work under radiation.
 Latch Up – minimal operation, supply current .
 Total Dose – radiation, full functionality test.

Each ADV202 must be placed in a socket ( all boards ).
 All
mounted components must be at least 0.5 cm far from the
ADV202.

SEU - no special Codec PCB design requirements.
Tests Requirements
Latch-Up:
 Only one ADV202 is mounted.
 No capacitors bigger than 0.1uF mounted.
 Connectors for external power supply must be present.
 External reset signal + reset on power up.
 All signals will be connected to static values.
 External clock signal.
Total Dose Requirements

Total Dose:
 All inputs tied high trough a pull up resistor.
 No active components present.
 Stand alone – all essential control signals are external.
 Five ADV202 are mounted .
 All outputs connected to half Vdd through voltage
division resistors.

2 different ORCAD schematics:
 SEU + Functionality.
 Latch-up + Total Loss ( mounted differently ).
Current Status
Finished design of the Codec Board, Codec Board ORCAD
Schematic.

Finished integrating Ethernet controller, writing web server
application.

Writing GUI client which connects PPC1, capable of sending
and receiving data – full duplex communication.


Establishing Rocket IO connection – almost finished.

Controller top design.
Future Plans

PCB layout – 4 weeks.

PCB manufacturing and testing – 6 weeks.

ORCAD for Latch-up and Total Dose PCB – 1 week.
In parallel:

Controller implementation + loopback – 6 weeks.

Controller and PCB integration – 4 weeks.

Establish real 1.2Gbps input stream – 6 weeks.
Enhance GUI application for supporting full
functionality – 2 weeks.
