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Characterization of a Large Format HgCdTe on
Silicon Focal Plane Array
B. Hanold, J. Lee, D. Figer – Rochester Institute of Technology
L. Mears, J. Bangs, E. Corrales, J. Getty, C. Keasler, M. Mitani – Raytheon Vision Systems
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Outline
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Project overview
Device design
Test setup
Characterization results
Going forward
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Project Overview
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HgCdTe detector cost can be reduced by using Si substrate instead of CZT
Project will develop low cost infrared detectors for astronomy with long term goal of
producing larger arrays enabled by using larger Si wafer
Project goal is to fabricate 2K x 2K MBE HgCdTe/Si detectors with competitive performance
Work is being funded by NSF and NASA to develop large format HgCdTe/Si detectors in
collaboration with Raytheon Vision Systems (RVS)
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Device Design Drivers
• Dark current and quantum efficiency identified as drivers for
HgCdTe/Si design improvements
• Multiple pixel designs need to be tested
• Large amount of testing required to select optimal design
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Variable Unit Cell (VUC) Devices
4 1K x 1K variable
unit cell detector die
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1K x 1K die fabricated with 4 unit cell
designs
Design allows direct comparison of
detector characteristics
VUC detector speeds design selection
and allows more time for optimization
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Detectors To Date
Detector
Format Cutt-off (µm) substrate
Virgo-9A
2K x 2K
1.7
CZT
Virgo-14
2K x 2K
4.9
Si
Virgo-V1
1K x 1K
2.5
Si
Virgo-V2
1K x 1K
2.5
Si
V1 and V2 are Variable Unit Cell (VUC) devices
None are substrate removed devices
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CfD received 4 detectors from RVS:
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SN: 9A, 14, V1, and V2
All bonded to Virgo ROICs
Current progress:
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Characterization of 2K x 2K HgCdTe/Si (SN: 14)
Characterization of 1K x 1K HgCdTe/Si (SN: V1)
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Rochester Imaging Detector Laboratory (RIDL)
in The Center for Detectors (CfD)
Test Results for an Array-Based GM_APD
Detector Before and After Irradiation
K. Kolb’s Poster L10
• 3 cryogenic test systems
• Computing cluster for data acquisition and reduction
running automated test suite
• Test systems integrate with telescope for on-sky
evaluation of detectors
• Test systems have been designed and used for
radiation testing
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Cryostat Detail
Outer Case
Detector Enclosure
Cold Plate
Filter Wheel
Electrical Connectors
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Detector Control Electronics
ARC Gen III controller used to operate the detectors
• Mezzanine current source board designed for
output buffer current supply
• ~7e- CDS noise - includes cabling
• Noise not increased significantly with addition
of current source circuit
J1
J2
C1
0.1u
J2N4393
R3
10
C2
0.1u
J2N4393
0
Through Hole
JFET
SMT JFET
V1
0
16.5
R1
6.5k
R2
6.5k
I
I
0
Mbreakp
Mbreakp
V
M1
V
M2
V6
V2
1.7
V3
9u
u
V5
2.0
0
2.0
0
0
0
Potentiometer
SMT resistor
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Virgo-14 Read Noise
Detector
Format Cutt-off (µm) substrate
Virgo-9A
2K x 2K
1.7
CZT
Virgo-14
2K x 2K
4.9
Si
Virgo-V1
1K x 1K
2.5
Si
Virgo-V2
1K x 1K
2.5
Si
V1 and V2 are Variable Unit Cell (VUC) devices
None are substrate removed devices
• 18 e- read noise CDS
• 5.5 e- read noise Fowler-16
• Noise may be improved with bias noise reduction
Virgo-14 Well Depth, Non-linearity, and Gain
• Well depth: 126 K e• Non-linearity terms:
– a = 1.712E-6
– b = -1.59E-11
countRate  1  aDN  bDN 2
VIRGO-14
Gain
ARC
5.9
25.1
ext. gain
int. gain MUX gain conv. gain conv. gain C cell
m V/ADU m V/ADU
11.69
3.26
13.23
3.66
gain
0.88
0.89
e - /ADU
2.50
0.63
m V/e -
fF
5.29 30.23
5.81 27.54
Virgo-14 Crosstalk
H2RG-015-5.0µm
Detector Temp. (K): 37.0
Number of images: 6
Number of Events: 1295
Crosstalk Results (%):
VIRGO-14-4.9µm
SB304-008-5.0µm
Detector Temp. (K): 30.0
Number of images: 2
Asymmetric crosstalk due
Numbersettling
of Events: 304
to incomplete
Crosstalk Results (%):
0.15
1.52
0.13
0.00
0.53
0.01
1.61
100.00
1.63
0.77
100.00
0.75
0.15
1.50
0.15
0.00
0.50
0.02
• Crosstalk measured using cosmic rays in dark exposures
• 3 x 3 grid shows crosstalk in nearest neighbors around central hit
• Results given in percentage of hit signal
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Virgo-14 Dark Current
Dark Current versus Temperature
1000.00
Dark Current (e-/s/pixel)
VIRGO-14
100.00
10.00
1.00
.02 e-/s/pixel
0.10
0.01
30
50
70
90
110
130
150
Temperature (K)
• Virgo-14 produced for a previous RVS project
• Device being used as benchmark to compare future devices against
• Currently measuring QE and validating 4.9 µm cut-off
Going Forward
• Project Milestones:
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Characterize VUC detectors
Characterize substrate removed VUC detectors
Select pixel design using VUC detector performance
Fabricate and characterize 2K x 2K substrate removed
MBE HgCdTe/Si device
• Long term goals for MBE HgCdTe/Si process:
– Scale design to 4K x 4K and 8K x 8K
– Reduce pixel pitch
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CfD Personnel
Don Figer
Joong Lee
Brandon Hanold
Iain Marcuson
Kim Kolb
P.I.
Engineer
Engineer
Engineer
PhD, IS
Matt Davis
Mike Every
Jon Zimmermann
Zach Mink
Kenneth Bean
Mike Shaw
MS, EE
BS, Physics
MS, EE
BS, EE
BS, ME
BS, EET
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Thank you for your attention.
Questions?
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