Transcript Stacked_Switches_MJB_V1

Stacked switch evolution and
development (part 2)
M.J. Barnes
TE-ABT - Beam Transfer R&D meeting #6, September 18th, 2014
1
Content
Part 2 of “Stacked Power Switches” by T. Kramer
& L. Ducimetière (28/09/2014)
• Inductive Adder versus Stacked MOSFETs;
• Experience and challenges of high voltage, fastswitching and/or high-repetition rate, stacked
Power MOSFETs;
•
•
•
•
•
Introduction;
Summary of some existing systems;
Parasitic capacitance;
Triggering (magnetic versus fibre optic);
Very short pulses.
2
Why Series Connect Power MOSFETs?
•
MOSFETs for fast switching typically have a maximum voltage rating of 1kV (used @ ~700V);
• Series stacking is required to achieve high voltage switches;
• Parallel connection may be required to achieve high currents.
“Standard” package
Low-Inductance (Fast Switching) package
(e.g. APT18M100B: 1 kV, 68 A pulsed,
~20 ns current rise, ~0.7 Ω on-state, 625 W,
Qgs=26 nC, Qgd=70 nC [@500 V]).
(e.g. DE375-102N12A: 1 kV, 72 A pulsed , ~3 ns current
rise, ~1 Ω on-state, 425 W, Qgs=16 nC, Qgd=42 nC
[@500 V]).
Notes:
treat specified power dissipation with healthy scepticism!
beware specified avalanche ratings!
3
Series MOSFETs versus Inductive Adder
Capacitor bank
Trigger
circuit
Trigger
circuit
Trigger
circuit
Trigger
circuit
Trigger
circuit
Trigger
circuit
Series MOSFET Swtches
Transformer core For trigger circuit
Pulse width
~350ns to DC
Pulse shaping
No
Trigger Circuit
Floating at pulsed high voltage
*: see talk by Janne Holma
Inductive adder*
For high voltage output
Max. limited by magnetic core
Yes
Referenced to ground
4
A Single Stacked MOSFET Switch
• DC storage capacitor is charged up
Trigger
circuit
Trigger
circuit
≈
Trigger
circuit
Trigger
circuit
to the required high voltage ( Vpk);
• The number of series modules,
including redundancy, is chosen
based on the MOSFET voltage rating
and required high voltage output;
• The trigger circuit is at MOSFET
source potential, i.e. floating with
respect to ground;
• The MOSFETs are turned on to
initiate the pulse (negative output
pulse in this example), connecting the
storage capacitor to the load;
• Here the load (RL) is resistive and
thus the load voltage naturally falls to
zero when the MOSFTs are turned
off.
Simplified Schematic of a stacked
MOSFET switch.
5
Push-Pull Stacked MOSFET Switch
PULL
PUSH
Trigger
circuit
3u
3d
Trigger
circuit
2u
2d
Trigger
circuit
Nu
Trigger
circuit
Trigger
circuit
Trigger
circuit
Cload
Nd
Trigger
circuit
Module
1u
Module
1d
Trigger
circuit
Simplified Schematic of a stacked
MOSFET switch.
• As per previous slide, but load is
capacitive and hence both a “push”
and “pull” MOSFET stacks are used,
to obtain fast rise AND fall times;
• Current flows only during the edges
of the pulse;
• The PUSH MOSFETs are turned on
to initiate the leading edge of the
output pulse (negative output in this
example) [PULL MOSFETs are OFF];
• PUSH MOSFETs are turned OFF:
subsequently the PULL MOSFETs
are turned on to initiate the trailing
edge of the pulse, connecting the
load to ground;
• The relative timing of turning-off a
stack of MOSFETs before the other
stack is turned-on is important.
6
Series Stacking of MOSFET Switches
Trigger
circuit
Parallel resistor for static (off-state)
voltage sharing: the same value is
used throughout the stack.
•
•
Parallel “fast-grading” capacitor
for dynamic voltage sharing: not
necessarily the same value
throughout the stack (see later
slides).
Ensure static and dynamic voltage sharing.
Design of trigger circuit (gate driver) is important and is
dependent upon several factors, including output pulse
requirements (e.g. maximum width and/or rise time).
7
Summary of MOSFET Based Kickers
Date
Built
Output
Pulse
Voltage
Rise & fall
time
(10%-90%)
Pulse Flattop
Width
Frequency Range
Load
(capacitive/resistive)
and comment
1994
5 kV
30 ns
250 ns to 1 s
1 Hz to 20 kHz
Cap / TRIUMF
1995
10 kV
40 ns
180 ns
Fixed: 1 MHz
Variable: up to 0.5 MHz
Cap / Prototype
2000
±10 kV
100 μs
20 ms to DC
DC to 10 Hz
Cap / TRIUMF
2001
−3.5 kV
63 ns
350 ns to DC
DC to 52 kHz
Cap / TRIUMF
2003
±12.5 kV
40 ns
160 ns to DC
DC to 77 kHz
Cap / PSI (MuLan
experiment)
3 MHz
2.2 MHz
Cap / TRIUMF (RFQ)
1 kHz
Res / ILC prototype
(droop < 0.001%)
2004
0.5 kV
0.6 kV
125 ns
125 ns
50% duty
50% duty
2005/6
4.6 kV
6 ns
2008/9
2.8 kV
2.5 ns
>140 ns fixed
Up to 50 Hz
Cap / Behlke switch –
CLIC tail-clipper
2011/12
12kV
Rise=100ns
Fall=~60 μs
Fixed: ~2 μs
Up to 1 kHz
Cap / CLIC RF
breakdown research*
*Now collaborating with Luis Redondo (U. of Lisbon) to develop a MOSFET based
Marx modulator with faster fall time and adjustable pulse flattop.
Note: Luc used 4 series MOSFETs in trigger amplifiers  3.5 kV pulses.
8
Stacking of Discrete Elements
1st stage
Advantages:
•
Modular - easy to change a PCB if required:
increases lifetime of stacked switch, (c.f.
Behlke switch which cannot be repaired);
2nd stage
•
MOSFETs can be chosen for particular
properties (e.g. low capacitance);
•
Design can be optimized for specifications,
e.g. high repetition rate (low capacitance) Final stage
and suitable heat-sinks on each power
semiconductor;
•
Experience: very low failure rate for an
appropriate design.
Disadvantages:
•
Design needs careful thought – not “off the
shelf”;
•
Modularity increases size;
•
Magnetic triggering generally limits
minimum pulse-width (~350 ns). Optical
triggering is very challenging.
Backplane with fast
grading capacitors
9
Fast and/or High-Repetition Rate Systems
PUSH
Trigger
circuit
Cload+ Cconnections
Nd
Linearized MOSFET DS capacitance,
for simplicity (includes fast grading [Cfg])
PULL
Cm(N)
Nu
Trigger
circuit
3u
Trigger
circuit
2u
Trigger
circuit
Cgnd
Trigger
circuit
3d
Cm(3)
Cgnd
Trigger
circuit
Trigger
circuit
2d
Module
1d
Cm(2)
Cgnd
Cm(1)
Module
1u
Trigger
circuit
• When the push stack turns-on, it must
charge its own (parasitic) capacitances, as
well as Cload, Cconnections, to Vchg. The
effective capacitance (Cm(N) and Ck) of the
off-state (PULL) stack must also be
charged. Thus minimize:
• Cconnections (e.g. coax cable length);
• Cm(N) (choose suitable MOSFET(s) and
minimize Cfg);
• Ck (low permittivity dielectrics [e.g. air],
optimize clearance to ground, optimize
distance between layers [but allow for
heat-sink and HV!]).
• Transient voltage distribution (Vm(N)) is
dependent upon k  k   Cgnd Cm ( N )  . For k <
0.05, equation can be expressed simply:
 N 1 
Vm ( N )  Vm (1) 1   ik 
 i 1 
• Cfg is minimized by having different
N 1
values for each level:
Simplified Schematic of a stacked
MOSFET switch.
C fg ( N )   i * Cgnd (i )
i 1
Note: beware during HV distribution measurements and interpreting results! 10
1000
950
900
850
800
750
700
650
600
550
500
450
400
350
300
250
200
150
100
50
0
Ceffective
Cincremental
Effective Capacitance (pF)
Capacitance [pF]
Example of Effective Capacitance
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
Cgnd=0.7pF
Cgnd=1.7pF
Cgnd=2.7pF
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Number of Levels
900
850
800
750
700
650
600
550
500
450
400
350
300
250
200
150
100
50
0
Drain-Source Voltage (V)
Measured voltage-dependent incremental
capacitance (Cincremental) and effective
capacitance (Ceffective) of a DE375-102N12A
MOSFET.
Effective Capacitance to ground of an offstate pull up stack of DE375-102N12A
MOSFETs (12.5 kV per stack) with
minimum values of fast-grading capacitors.
Note: 42pF 2*250 W for 12.5 kV @ 75 kHz.
Conclusion: minimize Cgnd (air insulated)
and, for unavoidably high Cgnd (because of
heat-sinks etc.), minimize the number of
levels (use high voltage MOSFETs and
sensible redundancy).
Note: for Behlke switches we have no control over the (internal) fast grading
values or ability to use individual heat-sinks…..
11
Magnetic Triggering (1994)
Ferrite
core
Primary
winding(s)
Diagnostic (no
feedback to controls)
Charge latch
HV
Outputs
D1N4448
D1N4448
IN1-
IN2IRFD110
MOSFET
D1N4448
D1N4448
OUT +
Sec ondary
Prim ary 2
Prim ary 1
Rs1
LED
Zs
Zs Zs
Zs
Zs
Zs
Rled
Rfg
D
IN1+
IN2+
G
Rdc g
APT 1004RBN
Zgs
Ferrite Core
S
Zs
Zs
Zs
Zs
Zs
Rdc g
Zs
Zgs
Cgs
Cfg
Cgs
Rdc g
IRFD110
Cfg
Rgs
Rfg
D1N4448
Rs2
Current path for
turning-on MOSFET
D1N4448
D1N4448
D1N4448
OUT -
Charge
latch
• Initial rise of MOSFET gate-source
voltage is well synchronized, in time,
for all series MOSFETs – good!;
• But triggering directly through a
ferrite transformer core can result in
“slow” switching of the MOSFET, due
to both source impedance (~3A) and
Miller capacitance of the MOSFET;
• Beware: voltage swing of the
MOSFET sources, during switching,
modifies the primary current and
thus the MOSFET gate current and
collapse of voltage across each
MOSFET!;
• Appropriate triggering can keep
MOSFET in the on-state indefinitely.
12
Optical Triggering (first system supplied
to MuLan experiment at PSI ~2003)
Ferrite: magnetic coupling to
supply energy for trigger system
Shield: FO receiver is
sensitive to electric field
Primary winding for
magnetic coupling
Issues with fibre-optics (FO)
for very fast switching:
•
FO receiver
MOSFET driver (up to 20A)
•
MOSFET
Shield: FO receiver is
sensitive to electric field
•
Fibre optic transmitter board for both stacks:
•
•
DC coupled FO receiver (not
AC FO, as typically used in
telecommunications) is needed
to minimize susceptibility to
erratic switching due to noise;
Propagation delay differs from
FO receiver to receiver and
must be compensated for;
Pulse width distortion of FO
receiver output (HFBR-2528
used here): contains an IC, but
significant PWD still occurs;
Any dust in FO system
increases rise-time of optical
pulse at receiver, changing
delay and PWD!;
FO cables are delicate and,
e.g. due to bending, the delay
of the cable can inadvertently
change.
13
Concept for Very Short Pulses, e.g. ILC
Charging
Resistor
Fast
Switch
L
C
(V)
D
S
L
L
C
D
C
([N-1]V/N)
S
D
S
MOSFETs cannot
typically be turned-on
and off fast enough
for very short pulses.
Output to
stripline &
matched
terminating
resistor
L
C
C
(V/N)
PFN
X X
HVDC
HVDC
Fast
switch
Z
Transmission
line
Z
Copt
Stripline plates
Z
Termination
resistor
Z
Beam
From second
pulse generator
Z
Z
Stacked MOSFET switch is its own PFL (delay line of limited length):
 
 
  L Z & N   N  L
Z
• For a given minimum inductance,
the delay of a 100 Ω line is less than
that of a 50 Ω line;
• A “delay-line” switch was configured
as ~100 Ω, terminated resistively in
100 Ω;
Note: pulse rise-time
and width increase with
DC supply voltage
(due to Miller charge).
Measured pulses for 3kV, 6kV, 9kV &
12.5kV DC supply (100 Ω PFL).
14
Summary re Series MOSFETs Switches
•
Significant experience with stacked MOSFETs (since 1994) for fast, high repetition-rate, switching,
generally with capacitive loads. Higher current versions can be built, e.g. with parallel MOSFETs,
but with increased capacitance ( higher switching losses);
•
Modular design results in significant reliability advantages w.r.t. a Behlke switch. In addition, for a
system designed in house, fast-grading and trigger circuits can be optimized;
•
In general, for fast or high rep-rate, design for a realistic minimum parasitic capacitance (e.g. air
dielectric) to minimize losses and switching times;
•
R&D of the latest generation MOSFETs, for pulsed power applications, is required.
•
Triggering circuit can be challenging – fibre optics have significant associated problems (e.g.
range of propagation delays through receivers and pulse width distortion): this needs further R&D
to identify improved solutions;
•
Do not switch MOSFET faster than necessary (limit gate current) to minimize problems with differences in
switching times and EM noise generation;
•
Heat removal from MOSFETs can be a significant issue, especially where a low capacitance
system is required (suggests small heat-sinks): this could benefit from further R&D;
•
R&D required for improved diagnostics (feedback to controls);
•
R&D recently commenced: MOSFET based Marx Generator “collaboration” with Luis Redondo (U.
of Lisbon).
•
R&D: application of Marx Generator technology to insulation testing for CLIC Klystron Modulators.
15
Switch technology overview
and CERN kicker applications
100
GTO ring gate
LHC-MKD
Peak current (kA)
Thyratron
10
PSB-TK
SPS-MKDV
GTO
SPS-MKDH
LHC-MKB
AD-Horn
PSB-EK
LHC-MKI
SPS-MKPi
SPS-MKP
PS-FAK
SPS-MKE
PS-TIK
1
FID
PSB-BI-DIS
IGBT
CLIC-DR
MOS
0.1
0.01
0.1
1
Rise time (us)
10
100
L. Ducimetière
16
Present CLIC HRR System
Supply Section
d.c. spark
system
.
PFL:
Td=2000ns
Charging Resistor
Z0=50W
4k7 W
Pulse Generator Section
CT: Bergoz:
Fast Switch:
CT-D0.5-B Coax Cable:
Behlke:
Z0=50W
HTS-181-25-B
12kV
Matching
Resistor
50W
Diode
Filter
capacitor
4.7nF
Matching
resistor
50W
Sample voltage without BD (right) and
measured current following BD at 12 kV (left)
The measured voltage rise-time
is less than 55 ns (10% - 90%)
and the voltage reduces below
1% of the applied voltage within
100 µs .
The measured current has a 2 µs "flat top" of ~120A
and a rise time of 14 ns (10% - 90%). The estimated
inductance, based on the 14 ns rise-time, is
approximately 320 nH.
Bleed
resistor
80kW
tip
Sample
 Reliability issues: occasional failure of Behlke
switch. Probably due to turning off high current
following a BD [trigger to switch-on is increased
in duration for 3 µs from the instant of a BD –
but a turn-off command can have been sent
≤200 ns before the BD …..].
 Limitations – no active pull down at present (23
µs fall time-constant  250 ns to 99%:
0.9930=0.74); system could be modified to
include active pull-down, but same reliability
issues – so better to explore other possibilities
(e.g. Marx Generator)
17
17
Principle of Marx Generator (1)
A Marx generator is an electrical circuit first described by Erwin Otto Marx in
1924. Its purpose is to generate a high-voltage pulse from a low-voltage DC
supply.
The circuit generates a high-voltage pulse by charging a number of capacitors
in parallel, then subsequently connecting them in series. This is illustrated
below for a 5 stage Marx.
1a) All the odd numbered MOSFETs/IGBTs (i.e. M1, M3, M5, …) are off.
1b) The capacitors (C1, C2 , … C5) are charged in parallel, from Vdc, by turning
on all the even numbered
MOSFETs/IGBTs (i.e. M2, M4, M6, …) [Vmarx ≈ 0 V]:
+
D1
Out
D2
D3
M1
+
Vdc
-
D4
M3
D5
M5
M7
M9
gate1
C1
C2
M2
C3
M4
C4
M6
VMarx
C5
M8
M10
gate2
Stored energy:
1
nCnVdc2
2
18
Principle of Marx Generator (2)
The circuit generates a high-voltage pulse by charging a number of capacitors
in parallel, then subsequently connecting them in series. This is illustrated
below for a 5 stage Marx.
2a) Capacitors C1, C2 , … C5 have been charged to Vdc in step (1b). All the
even numbered MOSFETs/IGBTs (i.e. M2, M4, M6, …) are then turned off.
2b) All the odd numbered MOSFETs/IGBTs (i.e. M1, M3, M5, …) are then turned
on, to connect the capacitors in series. VMARX ≈ 5Vdc
Out+
D1
D2
D3
M1
+
Vdc
-
D4
M3
D5
M5
M7
M9
gate1
C1
C2
M2
C3
M4
C4
M6
VMarx
C5
M8
M10
gate2
Load voltage: VMarx   nVdc
19
Example of each Marx Stage
MC7805CDTG
ON Semiconductor
The following circuit has been
implemented, by Luis Redondo,
using MOSFETs (in each
charge stage [M2] and pulse
stage [M1] two parallel
MOSFETs are used).
+15 V
1
7805
IN
OUT
+5 V
3
GND
2
330nF
330nF
GND2
In+
0.1uF
AVAGO
Technologies
+
4
DATA
Optic fibre 2 +5V 3
2
HFBR-2521Z GND 1
DATA
+
GND2
1
VDD
VDD
2
IN
OUT
TC1410 OUT
3
NC
4
GND
GND
8
7
6
5
VCC
IN
GND
IXRFD630
2
VCC
GND
gate1
OUT
Gate
GND
A
D1
M1
+
Microchip
K
GND
DE475102N21A
Out+
Drain
GND
GND
GND
GND
K
+
+
+
D
GND2
Gate
GND2
DE475102N21A
GND
A
Drain
GND
GND2
GND2
10uF
+
R10
+
K
A
D
Vcc=+15 V
4:20
+18 V
High
frequency
inverter
50 kHz
Dr
Dr
Dr
Dr
+
10uF
1
IN
R220
7815
OUT
GND2
MC7805CDTG
ON Semiconductor
MC7815CDTG
ON Semiconductor
3
1
IN
7805
GND
GND
2
2
OUT
3
+5 V
220nF
330nF
Out-
GND1
GND1
0.1uF
AVAGO
Technologies
DATA
Optic fibre 1 +5V
HFBR-2521Z GND
DATA
220nF
220nF
GND1
330nF
Z15 V
940C12P22K-F
CDE Cornell Dubilier
10uF
4
3
2
1
+
+
M2
+
Microchip
1
VDD
VDD
2
IN
OUT
TC1410 OUT
3
NC
4
GND
GND
8
7
6
5
VCC
IN
VCC
GND
IXRFD630
1
OUT
gate2
GND
GND
Gate
GND
DE475102N21A
Drain
GND
GND
GND
GND
K
+
GND1
+
+
D
GND1
Gate
GND
DE475102N21A
A
Drain
GND
GND1
Note: modular design so that, in
case of failure of a component, a
card can be replaced.
In-
Vcc bank capacitor of IXRFD630:
- 2 tantalum capacitors of 4.7uF, MULTICOMP, CB1H475M2DCB;
- 2 ceramic capacitors of 0.47uF, KEMET, C322C474M5U5TA;
- 2 ceramic capacitors of 0.1uF, AVX, AR205F104K4R*;
- 2 ceramic capacitors of 0.01uF, AVX, AR205F103K4R*;
- 2 ceramic capacitors of 0.001uF, AVX, AR205F102K4R*.
Other capacitors in circuit:
- 10uF tantalum capacitors , AVX, TAP106M035CCS;
- 100pF ceramic capacitors , AVX, AR211A101K4R;
- 470pF ceramic capacitors , AVX,12067A471JAT2A.
All capacitors with the same capacitance have a same reference.
D - Power diodes of STMicroelectronics – STTH1512G-TR
Dr - ultra-fast diodes of Vishay – BYG22D-E3/TR
20
20
1MΩ