Transcript I/O - Kahuna

ITFN 2601
Introduction to Operating
Systems
Lecture 19
Input/Output
Device Drivers
Agenda
I/O Hardware
Memory-Mapped & DMA
I/O Software Principles
Programmed, Interrupt-based, & DMA I/O
Device Drivers
Device Independent I/O
I/O Hardware
Block devices
Stores info in fixed-size blocks
Each independent & has own address
Ex. Drives
Character Devices
Stream-based
Ex. Printers, NICs, & mice
Various
Data
Rates
Device Controllers
Controls the device
Establishes a standard (IDE, SCSI, etc.)
Sits between the bus & device
Memory-Mapped I/O
CPU writes to registers on the controller
CPU can also write to data buffer on
controller (ex. video RAM)
Memory chunk in main RAM assigned to
corresponding space on controller
Write to memory chunk : this writes to
controller
Must be able to selectively disable cache!
“Listening In On” MemoryMapped I/O
All I/O controllers
listen on main bus
Multi-bus systems require
snooping or address filtering
DMA (Direct Memory Access)
Without DMA
With
DMA
I/O Software Principles
Device Independence
Uniform Naming
Error Handling
Synch vs. Asynch transfers
Buffering
Dedicated vs. Sharable resource/device
Programmed I/O
Disadvantage – ties up CPU
Interrupt-Driven I/O
Sending multiple blocks/chunks of data to
device
Why not do something while device
processes request
Let the device generate an interrupt when
request complete – then resume with next
block/chunk
Downside – too many interrupts!
DMA-based I/O
Let DMA handle the I/O transaction
Reduces need for interrupts
Downsides:
DMA controller is slower than CPU
CPU might be idle anyway 
Device Drivers
Code that provides an API to controller
Allows OS to access controller’s
registers, memory buffer, etc.
Must conform to OS standard for block or
character devices
Device
Driver
Location
Device Independent I/O
Uniform Interface for Drivers
OS to communicate w/out “hacking OS”
each time a device is added
Device Independent I/O
Buffering
Allow device to read/write data w/out having
to flood process w/ interrupts