Transcript Presentation by: Tom Hummel

OverSoC: A Framework for the
Exploration of RTOS for RSoC
Platforms
Presentation by
Tom Hummel
Background
 Complexity of Systems
 Parallelism
 Memory Management
 Concurrency
 Design Exploration
 Testing
 Validation
 Experimentation
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Motivation
 Prior Works
 Do not consider dynamic reconfiguration
 Do not provide OS-like resources and programming model
 Framework must provide exploration of
 Spatiotemporal Scheduling
 Reconfiguration and Resource Management
 Task Pre-emption and migration
 Inter-process communication
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Platform Exploration
 Hierarchal
 Top down design
 Evaluation at each level
 Performance Metrics
 User Defined
 SystemC Simulation Model
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System Description
 3 Elements
 Operating System
 Communication
 Memories and resources
 Processing
 GPU’s and DRA’s (Reconfig Blocks)
 Abstraction
 Layers are separated via API’s
 Evaluation and exploration at each level
 SystemC based simulation
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Refinement
 Process Element Refinement
 Virtual Nodes
 Functional Simulation
 Annotated Nodes
 Functional with timing constraints
 Cycle Accurate Nodes
 GPU and DRA simulations
 RTL Nodes
 Bit level accuracy
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Refinement
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RTOS Integration
 SystemC OS
 Highly Abstract
 Designed to be service and time
accurate
 Test various scheduling algorithms
and resource sharing methods
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 Communications
 Proxy like resource access
 Does not distinguish between
HW/SW
 Instantaneous Communication
Reconfiguration
 DRA Portioning
 Re-active Components
 Active Components
 Task Parameters
 Multilevel
 Allocation problem defined
as 3 levels for verification
 Provides determinism in case
HW version of task cannot
run, software can take over
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Reconfiguration
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DOGME Tool
 Design Exploration Tool
 Platform Design
 SystemC Code Generation
 Compilation and Simulation
 Analysis
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Processor Modeling
 Instruction Set Simulator
 AVR Instruction Set
 Easy to model and many compilers
 SystemC Based
 Cycle accurate exploration
 Predictable Execution
 Code broken into blocks which encapsulate system call free
code
 Improves simulation performance
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Validation
 Application
 Robotic Vision (Object Recognition)
 Nios-II on Cyclone-II SoC Platform
 uC/OS-II style services
 Ability of Framework
 Optimal number of CPU’s determined
 Task timing versus size of reconfigurable blocks
 Occupation rate of reconfigurable blocks
 Simulation time proportional to number of OS in system
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Opinion
 Long Paper
 Could be divided into 2-3 papers
 Poor Flow
 Description of DOGME platform is begun in middle of paper, yet
most of its features are elaborated in the experimental section
 Vague Descriptions
 Explanation of inter-OS communication not well described
 Communication Elements were not elaborated on
 ISS Architecture vs. Experimentation
 ISS Simulator uses AVR IS, however simulation was performed on a
NIOS-II. This discrepancy was not addressed
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References
 Miramond, B., Huck, E., Verdier, F., Benkhelifa, M. E. A.,
Granado, B., Aichouch, M., et al. (2009). OveRSoC : A
framework for the exploration of RTOS for RSoC platforms.
International Journal on Reconfigurable Computing,
2009(450607), 1-18.
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