Transcript globallinkx

High-Speed and Low-Power
On-Chip Global Link Using
Continuous-Time Linear Equalizer
Yulei Zhang1, James F. Buckwalter1, and Chung-Kuan Cheng2
1Dept.
of ECE, 2Dept. of CSE, UC San Diego, La Jolla, CA
19th Conference on Electrical Performance of Electronic Packaging and Systems
Oct 25, 2010 Austin, USA
Outline
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Introduction
Equalized On-Chip Global Link
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Driver Design for On-Chip Transmission-Line
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CTLE modeling
CTLE design example
Driver-Receiver Co-Design for Low Energy per Bit
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Guideline for tapered CML driver
Driver design example
Continuous-Time Linear Equalizer (CTLE) Design
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Overall structure
Basic working principle
Methodology
Overall link design example
Conclusion
2
Research Motivation
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Global interconnect planning becomes a challenge in
ultra-deep sub-macron (UDSM) process
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Performance gap between global wire and logic gates
Conventional buffer insertion brings in larger extra power
overhead
Uninterrupted wire configurations are used to tackle
the on-chip global communication issues
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On-chip T-lines to reduce interconnect power
Equalization to improve the bandwidth
State-of-the-art[Kim2009]
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2Gb/s/um, < 1pJ/b, signaling over 10mm global wire in 90nm
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Our Contributions
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Contributions
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Build up a novel equalized on-chip T-line structure for
global communication
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Tapered CML driver + CTLE receiver
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Accurate small-signal modeling on CTLE receiver to
improve the optimization quality
 A design methodology to achieve driver-wire-receiver cooptimization to reduce the total energy per bit
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Results of our design
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20Gbps signaling over 10mm, 2.2um-pitch on-chip T-line
11ps/mm latency and 0.2pJ/b energy per bit in 45nm
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Equalized On-Chip Global Link
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Overall structure
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Tapered current-mode logic (CML) drivers
Terminated differential on-chip T-line
Continuous-time linear equalizer (CTLE) receiver
Sense-amplifier based latch
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Basic Working Principle
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Tapered CML Driver
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T-line
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Differential wire w/ P/G shielding
Geometries (width, pitch) and termination resistance RT
CTLE Receiver
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Provide low-swing differential signals to driver T-line
Tapered factor u, number of stages N, fan-out X, final stage
current ISS, driver resistance RS
Recover signal and improve eye-quality
Load resistance RL, source degeneration resistance RD and
capacitance CD, over-drive voltage Vod.
Sense-amplifier based latch
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Synchronize and convert signal back to digital level
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Tapered CML Driver Design
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Output swing constraint
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Design guideline [Tsuchiya2006, Heydari2004]
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Begin from the final stage
For given VSW, output resistance RS
optimized with RT to increase eye-opening
 Transistor size
Need to design:
1) Output resistance RS
2) Tail current ISS
3) Size of transistors W
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Tapered factor u = 2.7 for delay reduction
Number of stages
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Each previous stage is designed backward
by scaling with the factor u
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CML Driver Study w/ Loaded T-line
Assume 45nm 1P11M CMOS
T-line built on M9 with M1 as reference
T = 1.2um, H = 3.5um (fixed)
Optimize W and S for eye-opening
Change of the eye-opening
with width for fixed 2um pitch
Change of the eye-opening with
pitch for equal width/spacing
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CML Driver Design Example
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Experimental observations
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Design methodology
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Optimal eye happens when width=spacing
Eye-opening improves with larger pitch
Choose the minimum pitch that satisfied the wire-end eyeopening requirement
Design example
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Accurate CTLE Modeling
Design Variables: RL, RD, CD, Vod(Size)
   (Vod ),    (Vod ), K  K (Vod )
gm  
I Bias
V  Vic  W  2 I Bias
1
, rds 
, Ibias  dd
,  
1.2
Vod
 I Bias
RL
 L  KVod
CSpara  1.5fF/um  W , CDpara  1.5fF/um W
CD  CDex  CSpara , CL  CLex  CDpara
[Hanumolu2005]
GainDC
Small Signal Circuit to derive H(s):
vin
G
D
gmvgs
rds ( RLCL  RD CD )  ( g m rds  1) RD RLCL  RL RDCD
( g m rds  1) RD  rds  RL
b
rds RD CD RLCL
( g m rds  1) RD  rds  RL
RL
CL
z 
S
RD
a
vout
rds
CD
1  sRD CD
1  as  bs 2
g m rds RL

( g m rds  1) RD  rds  RL
H ( s )  GainDC
1
RD CD
 p1  1/ a
 p2  a / b
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CTLE Modeling Validation
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Test case:10mm, 16mV-eye@wire-end
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Blue lines: simple modeling, not consider rds and parasitics
Red line: only consider rds
Black line: the proposed accurate model
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CTLE Design Example
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Observations of CTLE study
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Eye-opening improves with relaxed power constraints but tends
to be saturated
Design example
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Based on the pre-optimized CML driver + T-line design
Eye-opening improved by 4X after CTLE
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Driver-Receiver Co-Design
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Methodology
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Optimization Flow
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Optimize driver-wire-receiver together by setting Veye/Power as
the cost function
Choose pre-designed CML/T-line/CTLE as initial solution
Driver-to-receiver step-response generation based on SPICE
simulation and CTLE modeling
Eye-opening estimation based on step-response
SQP-based non-linear optimization
Variables: [ISS,RT,RL,RD,CD,Vod]
Performance Comparison
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Option A:Driver/Receiver independent design
Option B:Low-power driver/receiver co-design
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Low Energy-per-Bit Optimization Flow
Pre-designed CML driver
Pre-designed CTLE receiver
Driver-Receiver Co-Design Initial Solution
Change variables
[ISS,RT,RL,RD,CD,Vod]
Co-Design Cost Function Estimation
SPICE generated
T-line step response
Receiver Step-Response
using CTLE modeling
Cost-Function
Veye/Power
Step-Response Based
Eye Estimation
Internal SQP (Sequential Quadratic
Optimization) routine to generate best solution
Best set of design variables in terms of
overall energy-per-bit
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Simulated Eye Diagrams
Methodology A: driver/receiver separate design
Methodology B: driver/receiver co-design for low-power
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Summary of Performance Comparison
Methodology A
driver/receiver
separate design
Methodology B
driver/receiver codesign for low-power
RS/ohm
47
148
RT/ohm
94
1100
RL/ohm
440
890
RD/ohm
110
1430
CD/fF
680
150
Vod/mV
60
58
Eye-Opening@CTLE/mV 91
113
Power Consumption/mW 8.1
3.8
Note: driver/receiver co-design methodology uses much larger
driver/termination resistance to reduce power, but will close the eye-opening
at the driver output and wire-end. Final eye is recovered by fully utilizing CTLE.
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Conclusion
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We propose a novel equalized on-chip global link
using CML driver and CTLE receiver
Accurate modeling for CTLE is provided to achieve
<10% correlation error and will improve eye-opening
optimization quality
Our design achieves
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20Gbps signaling over 10mm, 2.2um-pitch on-chip T-line
11ps/mm latency and 0.2pJ/b energy
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Thank You!
Q&A
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