Transcript Academic training microelectronics nanoelectronics

12-14 January 2004
Pierre Jarron
Lecture 2
CERN EP-MIC
microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 1
microelectronics
nanoelectronics
monolithic pixel detectors
ACADEMIC TRAINING
Academic training
Nanoelectronics
3.
1.
2.
3.
4.
5.
Brief history of microelectronics
Evolution of microelectronics in HEP
Microelectronics at LEP
Microelectronics at LHC
Future trends of microelectronics
1.
2.
3.
4.
5.
6.
Is there an end to CMOS
Ultimate CMOS nanoscale technology
Introduction to mesoscopic physics
Quantum confinement, and electronic transport in nanowires
Quantum dots and Single Electron Tunneling (SET) Transistor
Nanoelectronic systems
1.
2.
3.
4.
5.
6.
Hybrid pixel detectors at LHC
Monolithic pixel on bulk CMOS
3D silicon detector
MAPS APS monolithic pixel detector
DEPFET monolithic pixel detector
Thin film on ASIC pixel detector
Trends in microelectronics and nanoelectronics
Monolithic pixel detector
microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 2
2.
Microelectronics and HEP instrumentation
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1.
Slides of the lectures
Acad-Tra_Micro-Nano_P.Jarron_2004_Lecture1.pps
With Java applet inverterFab.jar
Acad-Tra_Micro-Nano_P.Jarron_2004_Lecture2.pps
Acad-Tra_Micro-Nano_P.Jarron_2004_Lecture3.pps
microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 3
\\cern.ch\dfs\users\j\jarron\Public
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In NICE public account:
Future Trends
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microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 4
Accelerated scaling in 2001
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microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 5
Shrinking and mixing technologies
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microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 6
MOS device is becoming a nano-object
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microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 7
Not really planar!
The ultimate nanoscale MOS
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microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 8
End of CMOS? When?
Theoretical prediction
Quantum limit
Novel nanoscale MOS devices
Nanowire MOS device
The ultimate MOSFET
Will be theoretically reached in 2015
J. Meindl
Minimum switching energy/VDD of a Mosfet
Not a realistic VDD! minimum theoretical switching voltage inverter
VDD min

1 Q
Cd 
E

2 G min VDDmin , QG  q
S
min


 2UT Log  2 
 2UT Log 2  0.036VT 300K

Cox 

ES min  kT log 2  0.0179 eV at 300 K
Single electron MOSFET size
L2Gmin
1 QG2
ES 
 CG   ox
 LGmin
2 CG
tox
1
 tox 2  2
  q  for QG  1 electron
  ox

 2kTLog2  with tox  1.5nm , L  13.9nm


min
After J. von Neumann, theory of Self reproducing automata 1966, and J. Meindl,IEEE Vol. 35 No 10 October 2000
microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 9
Ebit  2kTLogN, N  2  Ebit  2kTLog2
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J. von Neumann
Thermodynamical minimum of energy per information bit
Towards charge quantum limit
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microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 10
MOSFET device fundamental limits
Colomb Blockade
Channel charge f(Lg)
10 electrons
At 15 nm
After J. Gauthier LETI
microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 11
Quantum confinement in a doped channel caused drain current oscillations
Discrete doping center caused Colomb blockade in channel
Limit of the quantum electronic charge approaches
Drain source tunneling < 5nm
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Fundamental quantum limits of CMOS
Nanoscale MOSFET device
Channel on SOI or SON
Double gate
GAA
FINFET
Remark
There are plenty of ideas
of novel nanoscale device
but no solution for interconnections
After Likharev 2000
microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 12
No high field in drain region to avoid SCE
Undoped channel to avoid coulomb blockade and doping fluctuation
Metal gate to avoid poly depletion and low threshold voltage
Channel conduction is ballistic
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Novel nanoscale device geometry
Suppression of Short Channel Effects
Gate
Source
Drain Source
Gate
Drain
Gate
Double-gate MOSFETs
GAA MOSFETs
Double-gate MOSFETs have been fabricated in
many research institutions.
microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 13
Stronger gate control
Three-dimensional gate structures
ACADEMIC TRAINING
It is difficult to suppress the short channel
effect in the traditional planar device structures.
Variations of Double-Gate MOSFETs
Gate
Gate
Gate
n
n
Si
n
n
Planar Double-Gate
IBM (2002
SSDM)
Vertical
Agere (2000
IEDM)
Si
Buried Oxide
Si-substrate
FinFET
Hitachi (Delta)
UC Berkeley (2001 IEDM)
IBM (2002 SSDM)
Intel (2002 SSDM)
microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 14
Si
S
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D
Ultimate CMOS Device process
•Semi-planar” SOI MOSFETs
•Suppression of short channel effect
•Finite body effect factor
•Quantum effects in narrow channel
MOSFET
microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 15
•10 nm Gate Length Regime
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Prof. Hiramoto’s Proposal /Tokyo
Requirements and issues
Large threshold voltage fluctuations
Adaptive Vth control will be essential
Metal gate and planar DG does not solve the problem
Need for a fourth terminal to control Vth
Substrate bias is the only solution
A device with a finite body effect factor for voltage
threshold control
microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 16
- Simple fabrication planar process.
FinFET rather than planar double-gate.
- Threshold voltage adjustment.
Metal gate, Work-function engineering.
ACADEMIC TRAINING
- Double-gate MOSFETs are good for
Short channel effects, high-drive current
- What are other requirements?
Semi-Planar SOI MOSFETs
Si
Buried Oxide
Si-substrate
Triangular Channel
Si
Si
Buried Oxide
Si-substrate
“Low” Fin
- Simple planar process.
- 3D gate structure for SCE suppression.
- Sufficient body effect from the backside.
-To compensate threshold voltage variations
-Utilize quantum ballistic transport
microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 17
Si
Gate
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Gate
Hiramoto’s sub 10nm MOS design
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Gate
Si
Si
Buried Oxide
Si-substrate
Triangular Channel
Gate
Si
Si
Buried Oxide
Si-substrate
“Low” Fin
microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 18
Semi-planar SOI MOSFET
solve
Short channel effects
Device Vt mismatch
Body effect factor
Profit from:
Quantum effects
Channel is nanowires in
parallel
SEM Images of a Channel Array
BOX
T. Saito et al, Si Nano WS, 2001.
microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 19
Channel
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Cross-sectional SEM image of an array of triangular channel
gate
200
n
180
Simulation
160
120
Vds=0.1V
tsoi=100nm
tox=13nm
Na=1x1015cm-3
100
Single-gate
140
80
n
n
tSOI Si
Box
Single-gate
Double-gate
Triangular wire
Triangular wire
60
40
0.1
0.2
0.4
Lg(mm)
n
0.6 0.8 1
- Covers only two sides of the triangle.
- Short channel effect is better than the double-gate.
T. Hiramoto, SOI Conference, 2001.
microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 20
Double-gate
tSOI Si
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Subthreshold factor (mV/dec)
1.Triangular nanowire channel - SCE
1.Subthreshold Characteristics
Id(A)
Single gate
(Lg=0.50mm)
Vds=1.5V
tox=13nm
tsoi=100nm
Na=1´1015cm-3
Triangular wire
(Lg=0.47mm)
-1.5
-1.0
-0.5
0.0
0.5
Vgs(V)
1.0
T. Hiramoto, SOI Conference, 2001.
1.5
microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 21
10-3
10-4
10-5
10-6
10-7
10-8
10-9
10-10
10-11
10-12
10-13
10-14
ACADEMIC TRAINING
Triangular wire channel MOSFETs show better sub
threshold characteristics than single-gate SOI MOSFETs.
2. Body Effect
n+
Csub
n+
Depletion layer
Vth
Vbs
slope
Vth0
0
DVth
DVbs
DVth
Log Ids
Ion1
Vbs1
Csub

Cg
Ioff1
Vbs2
Ioff2
Vg
Vth1
DVbs
Vbs
Vth2
Vdd
Vbs1 > Vbs2
microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 22

Cg CD
DVth
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Gate
2.Body effect in double Gate MOS
Si
n
n
Si
n
Ground Plane
n
Si
n
Box
Vbs
Large Cg
Csub = 0
S factor: Very Good
SCE:
Good
Zero
body
Small Cg
Small Csub
Good
Bad
Fair
T. Hiramoto 2002 SSDM
Large
Csub
Bad
Good
Good
microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 23
n
Single Gate SOI
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Planar Double Gate
3. Quantum Narrow Channel Effect
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microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 24
Quantum transport should be positively utilized
Higher Mobility in <100> Direction
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microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 25
H. Majima et al.
IEDM, 2001.
Quantum effects in MOS channel
gate
D
S
21020 e/cm3 =0.2 electrons/nm3 !
Multi-bands channel quantization
microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 26
Channel coupling reduction
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Channel coupling reduction
Increases the effective gate thickness
Carrier confinement quantization
Ballistic transport
multi-bands channel quantization
Single particle transport phenomena
NANOELECTRONICS
microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 27
is nanotechnology
 Introduction to mesoscopic physics
 Energy and space quantization
 Colomb blockade
 Quantum transport in nanowire
 Quantum dot
 SET
 SET circuits
 Carbon nanotubes
 Nanoelectronic systems
ACADEMIC TRAINING
 What
What is nanoelectronics?
There is plenty
of room at the bottom
microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 28
Nothing in the laws of
physics prevented us from
arranging atoms the way we
want: "...it is something, in
principle, that can be done;
but in practice, it has not
been done because we are
too big.
Device and technology based on
quantum mechanics
Mesoscopic objects are the size of the
Fermi length
Nanotechnology is about rearranging
atoms whichever way we want
Molecular nanotechnology or molecular
manufacturing
Human scale
ACADEMIC TRAINING
“There is plenty of room at the
bottom”
Richard Feynman - 1959
Top down and bottom up
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CO man !
Atomic
lattice
Alternative to planar process
still a Dream !
microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 29
We are too big, but we have instruments
small enough to handle atoms
Scanning Tunneling Microscope
Atomic force microscope
Scaling and mesoscopic physics
microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 30
At micron scale
classical physics
10nm to 100 nm
Mesoscopic physics
At nanometer scale
Quantum mechanism
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Properties dramatically change between 100nm to 1nm
Mesoscopic device
•human scale
Microscopic device
•classics physics
•crossover regime between
classic physics and quantum
physics
•Molecular device
•Quantum mechanics
DNA and 30nm MOSFET
Individual electrons observed size of
mesoscopic device comparable to the
spread of electron. Wavelength nature of
electron becomes important.
Complete space and energy quantization
Mesoscopic
devices
SETs
Classical
Quantum
mechanics
mechanics nanotubes
Quantum
dots
atoms molecules
MOSFET’s
microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 31
Mesoscopic device
Individual electrons unresolved current
flows as a fluid. Scaling is applicable
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Macroscopic device
Coulomb blockade in 50 nm MOS
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microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 32
Electronic transport: quantization, tunneling
In macroscopic (semi)conductors
•Individual electrons are NOT
resolved
•Linear scaling: conductivity and
geometry determines Ohm Law.
Mesoscopic devices, wires or dots
•Electrons are NOT point charge
• Tunnel junction quantizes current
flows
•Conduction in nanowires is not ohmic
Tunnel junction
microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 33
• Fermi gas, current flows like a fluid,
uniform charge density: n.e.Vd
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From classical to quantum transport
Ballistic transport in nanowire
microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 34
Free electron motion in propagation
direction,
Confinement in the 2 other dimensions
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Ohm Law’s is obsolete!
Quantum ballistic transport
microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 35
Only real part of the
wave function is shown
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Current flows governed by the time dependent Schrodinger equation
Quantum wave ?
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microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 36
Electron transport in nanowire
After Bell Labs 2001
microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 37
2-terminal measurement
Quantum resistance
4-terminal measurement
No resistance!
Resistance appears at the
at the contact points
with the electronic reservoir
Ballistic transport in nanowire
is resistance free!
ACADEMIC TRAINING
nanoscale solid-state devices
Electronic transport no scattering
Ballistic one-dimensional wire transverse motion quantized into discrete
modes
Longitudinal motion is free, electrons propagate freely
Value of the quantum resistance R0 = h/2e2 divided by the number of
occupied transverse modes.
A single mode, the resistance of a perfect wire is rather large: R0 = 13 k
But…
Insight in electron wavefunction
F  1nm to 50nm
2
2mEF
h2
T
Fermi wavelength defines
The effective size of the electron
Small for conductor
Large for semiconductor
Why wave interference plays a role is mesoscopic
devices?
Because phase coherence of electron wavefunction
is stable at nanoscopic scale.
Example of electron wave function in a 0.3mm quantum dot, Fermi length in the range of the
quantum dot size.
QD size should be smaller then average impurity spacing in the material
microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 38
F
2


kF
ACADEMIC TRAINING
Classical point charge,
Valid for macroscopic size
but not at atomic scale
Quantum effects in nano objects
Confinement of motion quantizes energy into
discrete states
smaller dot
macroscopic: scattering
mesoscopic wave interference
Tunneling controlled by gate voltage , SET
Coulomb blockade of tunneling
charging energy associated with isolated
Island causes Coulomb blockade.
 Energy cost q2/C.
 Discrete energy levels.
Ef Fermi level
Source Dot
Drain
Open QD, electrons move freely
Source Dot Drain
Closed QD,no propagation, barrier>Ef
microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 39
Energy quantization
ACADEMIC TRAINING
and space confinement
Mesoscopic
Devices Scattering
C
Nanostructure with size comparable to wavefunction
Quantum phase coherence of the wavefunction is kept
QD and SET
Quantum energy parameterization
Quantum confinement energy
microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 40
Fermi level Si
ACADEMIC TRAINING
Charging energy and quantum confinement energy
versus thermal energy
Coulomb Blockade of transport
nanoscale island: quantum dot
– Characterized by a quantum capacitance Ceff
2Ceff
R and C
Ne
Va
-e
Ne+1
q2
2Ceff
Total electron number of on QD/SET
Fluctuates by ONE N ± one electron
SINGLE electron Tunneling
Current flow becomes possible by tunneling
microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 41
» Island stored energy by Ne electrons in island N e q 2
2Ceff
» Addition of extra electron raises energy by
2
q
Charging energy
 kT
ACADEMIC TRAINING
 Isolated
Double tunnel junction – QD
Q1  C1V1
Va
RT Ceff
V1, 2

C

2 ,1
q2
DE 
, Dt  Rt Ceff
Ceff
1
C1Va  ne 
V2 
Ceff
q2
DEDt 
RT Ceff  h
Ceff
 ne 
Ceff
Es 
2
1
2
2
Q
Q

2C1 2C2
RT 
h
 25.8k
q2
q2
 kT Ceff  10aF T  300 K
2Ceff
Satisfy Heisenberg uncertainty and relation thermodynamic limit
Total charge stored on capacitors = Q
1,2=
C1,2 V1,2
Net charge stored on island Q = Q1 – Q2= ne
Capacitance of the island Ceff = C1+C2
Va does work transferring charge into and out of the island
When charge stored on either capacitor changes by tunneling,
additional polarization charge flows into the lead to maintain charge
balance equations
2
Energy change after a tunneling event

1, 2
DE
Work Ws, DQ is charge transferred by Va
qVa C1, 2
q


2Ceff
Ceff
WS   Va I t dt  Va DQ
microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 42
Q2  C2V2
1
C2Va  ne 
Ceff
V1 
ACADEMIC TRAINING
Heisenberg uncert.
Single electron tunneling transistor
ACADEMIC TRAINING
What is a single electron tunneling transistor?
Stability plot for the SET transistor in
Vb-Vg plane.
The shaded regions are stable regions.
Change in free energy after a tunnel event in junctions 1 and 2

DE1 

DE 2 
q q

  C2  CG Vb  CGVG  nq  q0 
Ceff  2

q
Ceff
q

  C1Vb  CGVG  nq  q0 
2

Coulomb oscillations in the SET transistor
microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 43
Double tunnel junction with an additional gate
Gate generates additional polarization charge QG
For most gate voltages ONE electron number is
allowed
Tunneling is blockaded
At other voltages QD is degenerate for q e
Current flow is possible
More explanations on SET…
ACADEMIC TRAINING
Electron transmitted
EN+1
E1
ER
e-
e-
EN
Source
Island
gate
Reservoir
Electron tunnels onto island
Source
Reservoir
Island
gate
Transport is blockaded
Source
Island
gate
Reservoir
Electron tunnels again
microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 44
Electrons may only flow by tunneling onto
the first unoccupied energy level EN+1.
Electrons will flow one by one if Vb is
increased such that E1>EN+1>ER, to change
the Fermi level (electrostatics) of the
island
Gate voltage Vg produce the same
tunneling conditions by lowering island
potential well
If EN+1> E1 transport is blockaded
Quantum dots - Artificial atoms
Simulation of electron wave functions of 3 “pancakes atoms” By solving Schrödinger's equation
____ ____ ____ ____ ____ E = 5
____ ____ ____ ____ E = 4
____ ____ ____ E = 3
____ ____ E = 2
____ E = 1
|0 0 ½>
|0 0 -½>
|1 0 ½>
For an excellent introduction to the quantum mechanics of the two-dimensional harmonic oscillator see French & Taylor, "An Introduction to Quantum Physics," pp 454 - 463, plus three exercises on page 469.
microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 45
This gives rise to a set of discrete and narrow electronic energy levels, similar to
those of atomic physics.
Essentially, artificial atoms (quantum dots) are small boxes holding a number of
electrons that may be varied at will.
As in real atoms, the electrons are attracted to a central location.
In a natural atom, this central location is a positively charged nucleus;
In an artificial atom, electrons are typically trapped in a bowl-like parabolic potential
well in which electrons tend to fall in towards the bottom of the bowl.
In most cases the nanostructures resemble "pancakes" in which the electrons are
restricted to motion in the x-y plane. Thus the appropriate potential is the two-dimensional
harmonic oscillator.
ACADEMIC TRAINING
A quantum dot (QD) is a nanostructure that can confine the motion of an
electron in all three spatial dimensions.
Artificial atoms – periodic table
As in atoms, Pauli exclusion principle
determines the number of electrons
of the QD system, 20 electrons in the
first 4 energy levels. New periodic
table can be built with artificial atoms.
nx
ny
E
n
l
E
0
0
1
0
0
1
1
0
2
0
+1
2
0
1
2
0
-1
2
1
1
3
0
+2
3
2
0
3
0
-2
3
0
2
3
1
0
3
3
0
4
0
+3
4
0
3
4
0
-3
4
1
2
4
1
+1
4
2
1
4
1
-1
4
Quantum corral
Quantum states of iron atoms placed on copper
After IBM
microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 46
Schrödinger's equation can be solved for this potential in both Cartesian and circular
coordinates, yielding the following expressions (in units of hn ) for the quantized
energy levels.
E(nx, ny) = nx + ny + 1
where nx = 0, 1, 2, 3, ...
and ny = 0, 1, 2, 3, ...
E(n, l ) = 2 n + | l | + 1
where n = 0, 1, 2, ....
and
l = 0, ±1, ±2, ...
ACADEMIC TRAINING
Quantum numbers and energies of the first 10 states
Operation of SET memory
ACADEMIC TRAINING
microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 47
Single electron memory integrated with CMOS
SET Memory devices that use fewer electrons per bit than current devices
Structures use between one and 10 electrons per bit, DRAM devices use half a million e/bit
Laterally formed nanowires produce CB oscillation at temperatures around 60K.
Lateral single-electron memory (L-SEM) cells containing MTJs formed using a heavily doped 50nm silicon nanowire integrated into the
memory node on a split-gate MOSFET.
During the write operation, electrons tunnel through the MTJ on the memory node by applying the write word line voltage (VWWL).
The stored voltage is read through the current in a split-gate MOSFET,
The two gates on either side of the central memory node act as switch transistors to connect the memory node to the data line, -50mV
('0' state) to +50mV ('1' state) the drain current increases from 1nA/µm to 1µA/µm, which is large enough to be detected by CMOS
sense amplifiers.
Write pulse of around 10ns.
These devices have much lower power dissipation than other memory devices, as around 100 000 times fewer
electrons are used for each operation.
After Cambridge University's Microelectronics Research Centre and Hitachi Cambridge Laboratory
microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 48
Experimental read/write measured om 2x3 cells
ACADEMIC TRAINING
a 3 X 3 memory array based on nanometer-scale Coulomb blockade (CB) memory devices.
SET operating at room temperature
ACADEMIC TRAINING
microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 49
Ct = ~3.6 x 10-19 F and Cg = ~3.5 x 10-19 F
K. Matsumoto, M. Ishii, J. Shirakashi, Y.
Oka, A. Kurokawa, and S. Ichimura,
Applied Physics Letters
Logic circuits with SET inverter
microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 50
Toshiba IEDM 2001, the 300K first SET logic based on
Hybridization of SET technology with CMOS
ACADEMIC TRAINING
Experimental
SET CMOS inverter
Circuit operates at
cryogenic temperature
After Uni Delft 1999.
Number of other circuits
have been developed.
Single Pass Electron Transistor(NTT)
ACADEMIC TRAINING
microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 51
Multifunctional SET logic (Toshiba)
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microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 52
ADC converter (NTT)
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microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 53
CNT properties
Discovered in 1991 by Iijima/Tsukuba
microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 54
1.2 -1.4 nm
1.33 g/cm3
2.83 Å
(12.9 k )-1
10-4 -cm
1013 A/m2
~ 2000 W/m/K
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Average Diameter of SWCNT's
Density: (10, 10) Armchair
Distance from opposite Carbon Atoms
Conductance Quantization
Resistivity
Maximum Current Density
Thermal Conductivity
M-SWNT wires and cross wires
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CNT is a new class of 1D conductor
SWNT 1.4nm diameter, single tube
MWNT, several tubes
After Richard Smiley
microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 55
Nanotube behaved as a ballistic nanowire with
quantum behavior. The MWNT conductance
jumped by increments of 1 G0 as additional
nanotubes were touched to the mercury
surface.
SWCNT transistor
microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 56
How to put the right tube at the
right place!
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Device design
Basic numbers
IBM CNTFET inverter
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AFM image After IBM. Published in Nano Letters August 2001
microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 57
A single nanotube bundle is positioned
over the gold electrodes to produce
two p-type CNTFETs in series. nCNTFET is produced by doping with
potassium through a window.
Characteristics of the resulting CNT voltage
inverter. Open red circles are raw data for
five different measurements on the same
device (V = ±2 V). The blue line is the average
of these five measurements. The thin
straight line corresponds to an output/input
gain of one.
Last news from MOS SWCNT
microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 58
– 300 cm2 V-1 s-1 have been
demonstrated for p-type Si
NWs
– 2,000–4,000 cm2 V-1 s-1 for
n-type InP NWs
– up to 20,000 cm2 V-1 s-1
for single-walled carbon
nanotubes.
– These nano FETs promise to
push the MOS nanoscale limit
with unprecedented
performance
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 Individual semiconductor
nanowires and single-walled
carbon nanotubes have been
used for nanoscale field-effect
transistors (FETs) with
performance comparable to or
exceeding that of the singlecrystal materials.
 In particular, carrier mobility
values of
Carrier mobility in SWCNT
To be published in 2004 in
Nano Letters
microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 59
Fits of the transconductance
reveals an electron mobility in
excess of 77 000 cm2/Vs; the
highest mobility measured on
any material so far.
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Ultra long semiconductor
nanotube transistors, 325
micron x 3.9 nm have been
recently fabricated – end of
2003.
SWCNT logic circuits
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After Charles M. Lieber Harvard, published in Science 2001
microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 60
Gold: $10/g
Carbon nanotube: $1500/g !! (Bucky/USA)
RF SET Transimpedance amplifier
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microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 61
Developed for single photon detection
Noise performance of SET-FET
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microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 62
Computing and nanoelectronics
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ENIAC, the first stored-program electronic computer, 1947.
The computer, a small section of which is shown here,
contained approximately 18 000 vacuum tubes and required
174 kilowatts of power to operate. The Intel 4004
microprocessor of 1971 could perform essentially the same
tasks as ENIAC, but required only a few watts of power.
HP Teramac 2000
After Stanley Williams/ Agilent
Teramac is a reconfigurable multi-architecture computer with 106 gates that operate at 1 MHz, or a total of
one trillion bit operations per second. Teramac is based on field-programmable gate arrays (FPGAs).
They are essentially lookup tables connected by a huge number of wires and switches that are arranged to
form crossbars, which allow you to connect any input with any output.
In principle, FPGAs substitute memory for logic whenever possible. As the number of resources available in a
computer increases, it makes more sense to store as many intermediate results as possible and just look
them up when needed.
microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 63
Eniac 1947
TERAMAC, crossbar computing concept
Less than a third of the gate arrays are used for lookup tables; most are
used only for their crossbar switches, to provide the massive
interconnectivity that defines the six-level hierarchy of the architecture.
Because of the very high degree of connectivity in Teramac, it was possible
to access nearly all of the good components in the system while ensuring
that none of the bad ones were used.
Perhaps the most amazing fact about Teramac is that it was comatose
at birth. Three-quarters of the FPGAs contain defects that would be fatal
for an isolated chip. In fact, the manufacturer gave those chips to the
creators of Teramac at no cost, charging only for the perfectly functioning
ones. Teramac contains a total of 220 000 wiring and gate defects--a
total of 3% of all of its resources. For the first 24 hours of its
existence, Teramac was connected to a workstation that performed a
series of tests to find out where the defective resources were. Those
locations were then written to a configuration table as being "in use," to
ensure that the defective components would not be accessed by a
running program.
The important lessons of Teramac for nanotechnology are that a system
does not have to be perfect to be very powerful, and that the more defects
a system can tolerate, the cheaper it will be to build.
After Joel Birnbaum and Stanley Williams Hewlett-Packard Laboratories.
microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 64
Redundancy by architecture
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Nanowires are assembled into crossbars
Organic molecules between crossing wires
serve as transistors
CNTFET switching array
Nanotechnology comes back to old technology!
June 11, 2002 Zurich
Using an innovative
nanotechnology, IBM
Zurich has
demonstrated a data
storage density of
one trillion bits per
square inch — 20
times higher than
the densest
magnetic storage
available today.
http://www.research.ibm.com/resources/news/20020611_millipede.shtml
microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 65
.
This technique is capable of achieving data
densities in the hundreds of Gb/in² range, well
beyond the expected limits for magnetic
recording (60–70 Gb/in²).
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A good old memory concept revisited: nano-mechanical memory
Nanoelectronics is on its way
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But not yet ready to play music!
microelectronics and nanoelectronics Pierre Jarron CERN MIC EP 13 th January 2004 66
Thanks for your attention
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