Transcript RIDGETOP-WEBINAR_SJ-BIST.ppsx

Interconnect Intermittency Detection with
SJ BIST™
Agenda
 What is SJ BIST?
 Interconnect Reliability – Background
 SJ BIST Basics
 SJ BIST Operation
 SJ BIST Application
 Summary & Conclusions
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What is SJ BIST?
 SJ BIST = Solder Joint Built-in Self-Test
 Original solution enabling the verification and
validation of solder joint interconnect reliability
 Originally developed for FPGA-BGA applications
 Can be applied to validate the integrity and reliability
of any type of interconnection
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BGA – PCB Relationship: Die, package, wiring, pins
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Defects: Location of Cracks/Fractures
 Corner pins likely to fail first
 High stress areas, and corners of the BGA package and die
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Solder Balls, Cracks and Fractures
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Mechanisms of Failure

Fatigue fractures (cracks) are
caused by thermo-mechanical
stress/strain

During periods of high stress,
fractured bumps tend to
momentarily open and cause
intermittent faults of high
resistance for periods of ns to
µs

Over time, contamination and
oxidation films occur on the
fractured faces: the effective
contact area becomes smaller
and smaller

Oxide-covered
area
Transient opens can be
detected by event detectors
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Mechanics of Failure
HALT results - Pulled FPGA – Damaged Solder Balls
Undamaged
Damaged: Cracked
Cracked, not detectable
Fractured, detectable
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Fractures and Intermittency
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Defects: Fractures & Intermittency
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Intermittent Faults
 Faults are intermittent: confirmed by CAVE, Auburn Univ.,
German automobile manufacturer, BAE Systems and other firms
 Occur during periods of increasing strain
 Multiple occurrences per cycle
 Industry standard: 200 ohms +, 200 ns +
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Intermittencies
 With present technology, reported electronic system problems
in the field cannot be duplicated at the service point or in the
lab
 “Three/Four-letter” words (CND, NTF, RTOK)
 Could Not Duplicate (CND)
 No Trouble Found (NTF)
 Retest OK (RTOK)
 50 to 80% of these CND/NTF/RTOK problem categories are
reported by service personnel.
 Major culprits – Solder joint intermittencies and NBTI effects in
deep submicron ICs
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SJ BIST Objectives & Features
 Objectives
 Detection of impending interconnect failures
 Unique in-situ testing in operating circuits
 Technology-independent
 Feature and Benefits
 Detects ball fractures prior to catastrophic failure
of circuit
 Provides actionable maintenance data
 Independently tested and verified
 Endorsed by leading automotive and aerospace
customers
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SJ BIST Implementation
Functional I/O
SJ BIST Control
SJ BIST I/O
SJ
BIST
Functional Circuitry
 SJ BIST runs concurrently with host circuit
 SJ BIST requires dedicated I/0
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SJ BIST Implementation
Functional I/O
SJ BIST Control
SJ BIST I/O
SJ
BIST
Functional Circuitry
 SJ BIST runs concurrently with host circuit
 SJ BIST requires dedicated I/0
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SJ BIST Implementation
Functional I/O
SJ BIST Control
SJ BIST I/O
SJ
BIST
Functional Circuitry
 SJ BIST runs concurrently with host circuit
 SJ BIST requires dedicated I/0
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SJ BIST™ Operation
 Similar to a simple memory test: W0 – R0; W1 – R1
 Runs concurrently with host circuit
 Verilog/VHDL core (patent pending)
 Each core tests two I/O pins
 Pins are externally wired together
 Small capacitor connected to the two pins
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SJ BIST Operation
Healthy Solder Joint
Writes a “1” and
reads a “1”
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SJ BIST Operation
Faulty Solder Joint
Writes a “1” but
reads a “0”
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SJ BIST Capacitor
 Function of operating frequency & desired sensitivity
300 Ohm
100 Ohm
10 Ohm
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SJ BIST
Interconnect path
SJ BIST Application
On-chip interconnects
Die to substrate (incl. bumps)
Requirement:
Interconnect path dedicated for SJ BIST
Die to board (incl. bumps & balls)
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SJ BIST Application
Testing On-chip Interconnect
Need for dedicated on-chip path between SJ BIST™ Observation pins
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SJ BIST Application
Testing Die to Substrate
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SJ BIST Application
Testing Die to Board
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SJ BIST Simulation Results
 LVTTL − Low Voltage TTL
Output
Low High
≤0.4V ≥2.4V
Input
Low
High
≤0.8V ≥2.0V
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SJ BIST Simulation Results
Clock = 50 MHz
 Charge pulse t=20 ns
 C1=57 pF (47 pF capacitor)+(10 pF of the
I/O port and wires)

The time constant =R1·C1 and t
determine the charge voltage
 In the prohibited zone (0.8 to 2.0 V) there
is guaranteed detection

Capacitor charging
t
R1C1
( e )
UC  U 0 1 

3.0V
3.0V
R1=175Ω
R1=700Ω
2.0V
2.0V
1.0V
1.0V
0V
0s
V(V1:+) V(C1:2)
20ns
40ns
Time
60ns
80ns
0V
0s
20ns
V(V1:+) V(C1:2)
40ns
60ns
80ns
Time
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SJ BIST Simulation Results
Voltage across the test capacitor
One bump is connected with a 700 Ω
resistor. So the time constant =R1·C1
increases and the test capacitor is
charged with only 0.8 V.
A logical ‘0‘ instead of a ‘1‘ is read, a
fault is detected.
700 Ω Fault: Same as electrical model and PSPICE simulation
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SJ BIST Application Results
 SJ BIST specifications

Sensitivity: as least as low as 100 Ω
 Resolution: guaranteed two clock periods
 Detectable intermittency: as short as ½ of a clock period
 50 MHz clock
 40-ns guaranteed detection
 10-ns detection possible
100 Ω fault
1 MHz clock
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SJ BIST Application Results
 Independent test results by German automotive firm
 Confirmed the same results as obtained by Ridgetop Group
 No false alarms
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SJ BIST I/O
 Input (Control)
 Clock, Enable & Reset
 Test Pins
 2 bidirectional I/O pins: TP0 & TP1
 Output (to host)
 Failure Flags (fault was detected on TP0/TP1)
 Active fault flags (fault is active on TP0/TP1 at the
moment of interrogation of SJ BIST)
 Failure counts (2 8-bit values related to number of
faults detected on TP0 and TP1 respectively)
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SJ BIST Summary
 Available as:
 Verilog/VHDL core
 Microcontroller code
 Requires dedicated I/O + capacitor
 Runs concurrently
 Interconnect reliability verification
 Process qualification
 Lifetime observation
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SJ BIST HALT for Process Qualification
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Contact Information
Ridgetop Group, Inc.
Hans Manhaeve
Office: +32 50 319273
[email protected]
3580 West Ina Rd.
Tucson, AZ 85741
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Ridgetop Products and
Services
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Ridgetop SPI Products & Services
nanoDFM Verification Monitors
PDKChek™ - Die-Level Process
Monitors
Mismatch: ∆VT,∆I(on), ∆R, ∆C,
YieldMaxx™ - Die-Level Variation
Visualization
ProChek Semiconductor Process
Characterization System
- NBTI
- TDDB
- Radiation
- VT Degradation
- PBTI
- Hot Carrier
- Stress Migration
- Electromigration
InstaBIST™ Test Cells
SJ-BIST BGA Solder Joint Built-in Test
ADC-BIST Self-testing Data Converters
Q-Star Test™ Current Monitors
IDDQ
IDDT
ISSQ
On-chip & On-board
Single- & multi-site
TopAct®
Radiation Transport
Analysis Acceleration
Sentinel Silicon Prognostic Cores
NBTI
TDDB
Hot Carrier
Radiation Exposure
InstaCell™ Mixed Signal Cores
ADC – Analog to Digital Converters
DAC – Digital to Analog Converters
Op Amps, References ,and
Comparators
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Cores
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MEMS
Custom instruments
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Advantages of PDKChek
PDKChek
Scribe Line Transistors
Uses test structure on the
host die
Requires additional test
fixture
Testing can occur preand post-packaging
Lost when wafers are sliced
Performs quick
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Delicate probe
measurement: inaccurate
and time-consuming
Measures parameters
that are useful to the
designer
May not directly measure
important parameters;
needs additional
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Data is applicationspecific
DUTs are extracted from the
host design
PDK models may not
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predictions
DLPM
Scribe Line
Transistor
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Example: Product Yield Analysis of 90nm Process
PDKChek
embedded in
the ADC
Example of GDSII Layout for the Ridgetop 14-bit Pipeline ADC
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Chip-Level Prognostic Solutions and Applications
Prognostic Cell
Library
Some Target Applications
NBTI Cell
Flash memory, SRAM
HCI Cell
ADCs, biasing circuits, analog,
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TDDB Cell
Flash memory
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Damascene process stress, high
current density application
Products described herein are
covered by U.S. patents:
7,239,163
7,196,294
7,271,608.
Other patents are pending.
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What is ProChek?
ProChek is an innovative low-cost technique to very rapidly characterize
the intrinsic reliability of deep submicron nanotechnology CMOS
processes (bulk CMOS, SOI and SiGe)
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Characteristics of ProChek

Targets bulk CMOS, SOI, SiGe reliability concerns


Test Coupon





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As little as 1 * 1 mm chip area
MPW for lower cost
32 – 1024 devices can be tested in parallel for maximum throughput
On-chip per transistor heaters to 325 °C, greatly reducing test time
Synthesizable (except for on-chip heaters) to speed deployment
Benchtop Tester


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NBTI / PBTI, TDDB, HC, EM, SM, TID
Fully programmable test conditions cover DC and AC stress cases
Portable and compact
ATE not needed
Host Controller



Easy-to-use software GUI
Rich suite of built-in reliability test templates
Data processing capabilities
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InstaCell™ IP Core Library
The cores provided by Ridgetop are "Silicon Proven" and
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Design Services
Ridgetop maintains a complete Cadence design flow, and has designed circuitry down to
the 45 nm process node. Ridgetop also has a line of predesigned and characterized IP
blocks that can be used to accelerate the time-to-market for your systems. Examples
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Our design services include:









Analog/mixed-signal and gate array integrated circuits with varying process nodes of 0.5 μm
down to 45 nm
High-speed, high performance, high linearity ADC and DAC design
Fuel Cell and Battery Management System components
FPGA-based designs, from basic specification to gate level, with timing analysis and
programming
IP blocks of specialized functionality
Modeling and simulation
Completion of back-end design from existing EDIF/SPICE to GDSII layout
Rescaling “legacy” designs to smaller process geometries
Radiation-hardened/foundry-specific designs
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Q-Star Test
 IDDQ ,IDDT, ISSQ and other precision
current measurement
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 Developed by Ridgetop Europe
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Q-Star Test Measurement Solutions
 Static (Quiescent) Current Measurement Instruments (IDDQ /ISSQ)
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Standard and advanced IDDQ tests
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Dynamic and transient (IDDT) current tests
Power profiling of circuits and systems
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…
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Why Ridgetop?
Domain Expertise
(Expansive portfolio
of electronic
prognostic solutions)
IP Easily Configured
to Target
Applications
(Seamless integration
and porting)
World Leaders in
Electronic
Prognostics
Customer Service
(Dedicated service
and support
personnel for on
demand assistance)
(Awarded most gov’t
contracts)
World Class
Engineering Staff
(All project
contributors PhD or
advanced degree)
Ridgetop
Group
Delivers
Commitment to
Innovation
(Strive to
improve/upgrade
existing IP)
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For more information about Ridgetop’s
products and capabilities please visit:
www.RidgetopGroup.com
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