Transcript Slides - Agenda INFN

Radiation- tolerant front-end electronics:
from the AToM chip to 65 nm CMOS
Valerio Re
INFN
Università di Bergamo
Sezione di Pavia
Dipartimento di Ingegneria e Scienze Applicate
Detecting Signals into the Noise. In Memoriam: Franco Manfredi...
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Detecting Signals into the Noise. In
Memoriam: Franco Manfredi
05 December 2016 Università degli Studi di
Pavia
Europe/Rome timezone
V. Re – in memoriam Franco Manfredi, Pavia, December 5, 2016
The art of low-noise front-end electronics and the
problem of radiation tolerance in the work of Franco
“The obvious trend towards a higher luminosity in the beams of the
accelerators and higher intensities in the sources of synchrotron
radiation will bring about more serious problems in the domain of
radiation effects and radiation hardness of materials and devices. As
already observed, this is going to be an extremely challenging area”
(F. Manfredi, Considerations on the 11th European Symposium on Semiconductor
Detectors, NIM A, 2010)
In the course of three decades, since 1980’s, rad-hard front-end
electronics for silicon detectors in particle physics experiments has
been based on technology and design choices, following the evolution of
microelectronic processes
Franco Manfredi gave an essential contribution to the understanding
of radiation effects on the noise performance of front-end devices
and to the development of techniques enabling readout electronics to
operate with a large signal-to-noise ratio at high radiation levels
V. Re – in memoriam Franco Manfredi, Pavia, December 5, 2016
2
JFETs as rad-hard devices
As a device based on the drift of majority carriers in the silicon
bulk, the JFET has an intrinsically high degree of tolerance to
ionizing radiation, which mostly affects silicon dioxide regions
(or other dielectrics).
Old CMOS technologies, with a thick gate oxide, were extremely
sensitive to ionizing radiation (even at a few tens of a krad).
Franco was proactive in the development of monolithic
technologies based on the JFET as a low-noise, rad-hard device,
addressing the radiation tolerance requirements of strip detector
front-end electronics at LEP and then at LHC
V. Re – in memoriam Franco Manfredi, Pavia, December 5, 2016
3
JFETs as rad-hard devices: the LEP environment
“The JFET as input device in the preamplifier has over a CMOS
transistor the advantage of a smaller spectral power density in the 1/f
term of the series noise source…Radiation degrades the noise
performance of a JFET to a lesser extent than it does for a MOSFET”.
(F. Manfredi et al, On the design of a JFET-CMOS front-end for low noise data
acquisition from microstrip detectors, NIM A, 1988)
CMOS-compatible JFET in the
Fraunhofer IMS Duisburg technology
V. Re – in memoriam Franco Manfredi, Pavia, December 5, 2016
4
JFETs as rad-hard devices: the LEP environment
“It became clear that long lasting design criteria had to ensure a
sufficient degree of radiation tolerance….The analysis of radiation
effects…leads to the decision of using the NJFET at the preamplifier
input and for all functions where a low 1/f noise is required. P-channel
MOSFETs are adopted as complementary elements for the N-channel
JFET.”
(F. Manfredi et al, Evolution in the criteria that underlie the design of a
monolithic preamplifier system for microstrip detectors, NIM A, 1990)
V. Re – in memoriam Franco Manfredi, Pavia, December 5, 2016
5
JFETs as rad-hard devices: the LHC environment
“Experiments at new high luminosity colliders (SSC, LHC) set most severe
constraints both on operating speed and radiation tolerance of the analog
processors. Different steps had to be taken, in order to extend the JFET-CMOS
technology, which is intrinsically radiation hard, to front-end systems for these
environments”
(F. Manfredi et al, JFET-CMOS process to meet the requirements of tracking applications
at short processing times, NIM A, 1994)
V. Re – in memoriam Franco Manfredi, Pavia, December 5, 2016
6
Noise in irradiated JFETs
“After irradiation, two Lorentzian noise terms appear. The white noise, which still
dominates at high frequencies, does not show any appreciable degradation”
(F. Manfredi et al, JFET-CMOS process to meet the requirements of tracking applications at short
processing times, NIM A, 1994)
“The characteristic frequencies of Lorentzian noise … occur at much lower
(values) in the P-channel than in the N-channel device. Although the P device has
a larger channel thermal noise before and after irradiation, there is a broad
frequency range where the irradiated P-device features less noise than the
irradiated N-device”
(F. Manfredi et al, “Trends in the design of front-end systems for room temperature solid state
detectors”, IEEE TNS, 2004)
Before irradiation
1 Mrad TID,
60Co
V. Re – in memoriam Franco Manfredi, Pavia, December 5, 2016
g-rays
7
Rad-hard CMOS
In the 90’s, high density front-end integrated circuits were required for the
readout of high granularity silicon vertex detectors (microstrips, and then
pixels), with 105-106 readout channels.
The integration of the analog front-end with high performance digital circuits
for sparsified readout, data storage and transmission was made possible by
CMOS technology scaling to the submicron region.
Special rad-hard CMOS processes were very interesting in view of the design
of readout electronics for collider experiments with increasing luminosity.
Rad-hard CMOS was based on a combination of process and layout techniques,
among which:
- Increased NMOS threshold voltage to account for radiation-induced shifts
- Increased isolation spacing between NMOSFETs to prevent TID induced
leakage
- Guard band diffusions around n-wells
- ….
V. Re – in memoriam Franco Manfredi, Pavia, December 5, 2016
8
The BaBar SVT and the AToM chip
The Honeywell 0.8 µm bulk CMOS process was selected for the CMOS readout
integrated circuit for the Silicon Vertex Tracker of the BaBAR experiment at
SLAC.
From May 1999 the rad-hard AToM chip
operated with the Silicon Vertex
Tracker in the BaBar experiment at the
collider PEP-II (SLAC).
The SVT consisted of 5 layers of
double-sided AC coupled microstrip
detectors surrounding the IP and
distributed at radii ranging from 3.3 cm
to 14 cm. The charge collected on the
strips was read out by 150,000 channel
of front-end electronics mounted at
both sides of the detector modules.
V. Re – in memoriam Franco Manfredi, Pavia, December 5, 2016
9
AToM: 128-channel CMOS IC
• It retains the analog information of the charge induced on the detector
electrodes
low noise amplification and shaping (selectable gain and peaking time, operation on
both detector signal polarities)
• It has been designed for a real random operation, without any external
synchronization
• It can simultanueously acquire and process the incoming analog signals and
build up and serially transmit derandomized streams of data relevant to
previous events
• The A/D conversion is based on the Time-over-Threshold technique
Two versions:
in radiation soft technology
(HP CMOS26G 0.8 µm)
in radiation hard technology
(required to stand 1 Mrad TID)
(Honeywell RICMOS IV 0.8 µm
bulk CMOS)
• polarity selection (connection to detector n-side
and p-side)
• Charge sensitivity: 100 mV/fC (radsoft)
Gain selection (150 mV/fC - 250 mV/fC) (radhard)
• Peaking time selection (100 - 200 - 300 - 400 ns)
• Low power: 4mW/channel
1.5 mW/channel in the analog section
•chip size: 5.7x8.3mm (330000 devices)
• radiation damage: < 10% @ 1Mrad (radhard)
V. Re – in memoriam Franco Manfredi, Pavia, December 5, 2016
Time-over-Threshold (ToT) approach
to analog-to-pulse width conversion
with a compression-type characteristic
CF
Q.d
CD
PREAMPLIFIER
SHAPER
COMPARATOR
Vth
A very interesting study
by Franco et al about
the effect of electronic
noise on the
measurement of the
Time Over Threshold:
“Noise limits in a
front-end system
based on time-overthreshold signal
processing”, NIM
A439,2000
“The noise analysis has
provided an insight into
the behavior of a ToT
processor as compared
to a conventional linear
processor. The ToT
principle is proven to
yield a viable approach
to the realization of a
charge measuring
system with rangecompression features”
V. Re – in memoriam Franco Manfredi, Pavia, December 5, 2016
Simplified diagram of the analog signal processing
channel in the AToM chip
V. Re – in memoriam Franco Manfredi, Pavia, December 5, 2016
Charge-sensitive preamplifier in the AToM chip
+5V
VP
M2
M1
M3
V IR
VN
M4
M8
M5
VGSELB
VGSEL
M50
+5V
M51
M14
VREF
OUT
VP
M10
Mc1
Mc1b
M20 M17
+2V
M18a
IN
VN
M13
M26
M24
M15
M18
Mc5
VI1
M22
M18b
The front-end element M13 is
a PMOSFET with a gate width
of 2500 µm and a gate length
of 1.2 µm.
The current through it is
about 250 µA. At this current
M13 features a
transconductance above 3 mS.
The size of M13 is chosen in
order to work, with an
acceptable mismatch, at
detector capacitances ranging
from 10 pF in the case of the
shortest strips to about 35 pF
in the case of the longest ones.
V. Re – in memoriam Franco Manfredi, Pavia, December 5, 2016
Noise [e rms]
AToM rad-soft
0 krad
10 krad
Irradiation with 60Co
g-rays
25 krad
50 krad
Suitable degree of
radiation tolerance in
applications where
radiation levels are
much lower than in high
energy physics
experiments at
colliders
Capacitance [pF]
V. Re – in memoriam Franco Manfredi, Pavia, December 5, 2016
AToM rad-hard
ENC variation at CD = 12 pF
after irradiation with 60Co g-rays
High gain setting, n-side
V. Re – in memoriam Franco Manfredi, Pavia, December 5, 2016
Evolution of CMOS technologies and increasing
demands on detector granularity, readout
speed and radiation hardness
The result of a shorter gate and a thinner gate
oxide is a remarkable improvement in noise and
radiation hardness features of the CMOS
processes such as to make them fully adequate
for front-end design”
P.F. Manfredi et al, “Trends in the design of front-end
systems for room temperature solid state detectors”,
IEEE TNS, 2004
PMOSFETs from
three different
CMOS generations
V. Re – in memoriam Franco Manfredi, Pavia, December 5, 2016
16
CMOS scaling and radiation tolerance
• Most of rad-hard CMOS technologies required an increased process
complexity and degraded circuit performance and density relative to
commercial bulk CMOS.
• Scaling of CMOS technologies brought along an increased level of
Hardening by layout
radiation hardness, thanks to gate oxide thinning: in thin oxides (few
nm) radiation-induced positive charge is removed by tunneling.
• Lateral isolation oxides were (and are) still thick and radiation-soft, but
this can be cured in NMOSFETs by using enclosed layout transistors.
SOURCE
GATE
Leakage
paths
DRAIN
• This evolution led to the widespread and very successful adoption of the
quarter micron CMOS node for HEP experiments at LHC and elsewhere
DRAIN
GATE
SOURCE
V. Re – in memoriam Franco Manfredi, Pavia, December 5, 2016
L. Ratti, Ionizing Radiation and Single Event Effects in Electronic Devices and Circuits – Legnaro, March 25th 2015
17
The FSSR2 chip
-
The analog front-end of the 128-channel FSSR2 chip can be seen as a a kind of
adaptation of the AToM chip front-end to 0.25 µm CMOS.
-
This chip was originally designed for the readout of silicon strip detectors in the
BTeV experiment. It is currently used in a beam test facility at Fermilab and for
the readout of strip detectors in the CLAS12 experiment at Jefferson Lab.
-
Franco played an essential role in establishing the Fermilab – INFN Pavia
collaboration that designed this chip.
7.5 mm x 5 mm,
input pads with
50 µm pitch
Front-End
Core Logic
Programming
Interface
Data output
Interface
V. Re – in memoriam Franco Manfredi, Pavia, December 5, 2016
18
FSSR2 analog channels
Preamplifier
Programmable Gain
Cf1
Programmable
Baseline
Restorer
Cf
Bias
+
Gf
CD
CAC
Hit/NoHit Discriminator
Threshold
circuit
Shaper
CR-(RC)2
-
To 3-bit Flash ADC
BLR
Single-ended/
Differential
conversion
Cinj
Test Input
(from Internal
Pulser)
Programmable
Peaking time
Threshold DAC
(chip wide)
V. Re – in memoriam Franco Manfredi, Pavia, December 5, 2016
Comparator
Vth
+
Kill
Shaper and BLR response
Charge sensitivity at
shaper output:
Low gain: 120 mV/fC
High gain: 160 mV/fC
0
0
shaper output
tP = 65 ns
-0.05
tP = 100 ns
tP = 125 ns
BLR output
OUT
-0.05
(V)
tP = 85 ns
V
Shaper output (V)
65 ns
t = 85 ns
P
-0.1
125 ns
High gain setting
Low gain setting
-0.1
-0.15
0
100
200
300
400
500
600
700
800
0
0.5
1
Time (ns)
V. Re – in memoriam Franco Manfredi, Pavia, December 5, 2016
1.5
Time (s)
2
2.5
3
Equivalent Noise Charge
2000
BLR selected
BLR deselected ENC = 200 + 25 e/pF
1500
ENC [e rms]
ENC = 230 + 28 e/pF
The BLR improves the
threshold dispersion
(AC coupling), but
increases noise
1000
However, ENC is well
below the spec value of
1000 e rms at CD = 20 pF.
500
Peaking time 85 ns
0
0
10
20
30
40
50
CD [pF]
V. Re – in memoriam Franco Manfredi, Pavia, December 5, 2016
Radiation tolerance
FSSR prototype

Irradiation with 27 MeV protons to a 1.9x1013 cm-2 fluence, corresponding to
a total ionizing dose of 5 MRad

After irradiation the chip remains fully functional with very little (< 10 %)
degradation of critical parameters such as ENC and threshold dispersion
FSSR2

Irradiation with 60Co g-rays to a total ionizing dose of 20 Mrad (no bias
applied during irradiation)

Chip fully functional after irradiation; noise and charge sensitivity are not
affected

Threshold dispersion with BLR selected increases by about 15 %
(remains below the spec value of 500 e rms)
V. Re – in memoriam Franco Manfredi, Pavia, December 5, 2016
Nanoscale CMOS and rad-hard front-end
chips for silicon pixel sensors
• The development of small pitch pixel detectors operating at extremely
high data rates and radiation levels and the enhanced performance of
digital circuits led our community towards nanoscale CMOS technologies.
• Today the focus is on the 65 nm CMOS node for the readout of pixels at
the High Luminosity LHC and at the next generation of light sources
(FEL).
• Front-end electronics has to retain excellent noise performance after
the exposure to extremely high radiation levels
• Digital figures of merit (speed, density, power dissipation) are driving
the evolution of CMOS technologies. For analog applications in which
speed and density are important, scaling can be in principle beneficial,
but what about critical performance parameters such as noise, gain,
radiation hardness…?
• In very aggressive low-power designs, small pixel cells (≤ 50 µm x 50 µm)
can contain just a reduced (“shaperless”) version of the analog front-end
V. Re – in memoriam Franco Manfredi, Pavia, December 5, 2016
23
General schematics of a pixel analog
front-end in 65 nm CMOS
Circuit for charge
restoration on the
feedback capacitor
CF
SENSOR
Q.d
Threshold adjustment by
DAC or autozero;
amplitude information by
ToT or Flash ADC
SHAPER
DISCRIMINATOR
CD
Vth
PREAMPLIFIER
PA forward stage: high gain, low
noise
Vth
ToT clock transmitted by
the chip periphery, or
generated by a locally
triggered oscillator
Trend is to skip the shaping stage in the
Charge restoration: handle
RD 53 HL-LHC pixel cell, mostly because of
sensor leakage current after
power constraints (noise filtering in the
extreme irradiation levels (max. preamplifier, or correlated double sampling
V. Re2–) in memoriam Franco
Pavia, December 5,
2016 )
20 nA at 2x1016 n/cm
at Manfredi,
the discriminator
input
How the analog channel may look like in a HL-LHC pixel readout
INFN-Pavia
IK/2
vout
CD
+
CF
VREF
Itr=Gm vout
Ith
IDAC
IK
AND
•
Single amplification stage for minimum power dissipation
•
Krummenacher feedback to comply with the expected
large increase in the detector leakage current
•
High speed, low power current comparator
•
Relatively slow ToT clock – 80 MHz
•
5 bit ToT
counter
• 30000 electron maximum input
charge, ~450 mV preamplifier output
dynamic range
5 bit counter – 400 ns maximum time over threshold • Selectable gain and recovery current
V. Re – in memoriam Franco Manfredi, Pavia, December 5, 2016
25
Noise in NMOS:
CMOS generations from 250 nm to 65 nm
1/2
Noise Voltage Spectrum [nV/Hz ]
100
1/f noise has approximately the same magnitude (for a same WLCOX)
across different CMOS generations. White noise has also very similar
properties (weak/moderate inversion).
1/f noise
K
2 (f) 
f
W/L = 2000/0.45, 250 nm process
S1/f
W/L = 1000/0.5, 130 nm process
COX WLf  f
W/L = 600/0.5, 90 nm process
W/L = 600/0.35, 65 nm process
10
• kf 1/f noise parameter
• αf 1/f noise slope-related
coefficient
C = 6 pF
IN
I = 100 A
Channel thermal noise
D
NMOS
1
10
3
10
4
10
5
10
Frequency [Hz]
6
10
7
10
8
4k T
S2W  B ,
gm
• kB Boltzmann’s constant
   W ng
• γ channel thermal noise
coefficient
• T absolute temperature
• αw excess noise coefficient
In weak g  ID
m
inversion:
nVT
V. Re – in memoriam Franco Manfredi, Pavia, December 5, 2016
26
1/f noise: NMOS vs PMOS
In bulk CMOS, the fact that PMOSFETs feature a smaller 1/f noise
with respect to equally sized NMOSFETs was generally related to
buried channel conduction.
In deep submicron processes, it was expected that the PMOS would
behave as a surface channel device, rather than a buried channel one
as in older CMOS generations.
With an inversion layer closer to the oxide interface, 1/f noise is
expected to increase. Ultimately, PMOSFETs should feature the same
1/f noise properties as NMOSFETs. However, this was not observed
in CMOS generations down to 130 nm and 90 nm.
A possible interpretation can be related to the different interaction
of electrons (NMOS) and holes (PMOS) with traps in the gate
dielectric (different barrier energies experienced by holes and
electrons across the Si/SiO2 interface) .
V. Re – in memoriam Franco Manfredi, Pavia, December 5, 2016
27
65 nm LP process: 1/f noise
In the 65 nm LP process by Foundry B, NMOS and PMOS have similar 1/f noise
(especially longer transistors).
Noise Voltage Spectrum [nV/Hz ]
100
100
1/2
1/2
Noise Voltage Spectrum [nV/Hz ]
This could be explained by a “surface channel” behavior for both devices, and/or
by the fact that the gate dielectric nitridation decreases the barrier energy
experienced by holes across the silicon-dielectric interface. This would make it
easier for the PMOS channel to exchange charges with oxide traps.
NMOS
PMOS
10
65 nm transistors W/L=600/0.35
@ ID=50 A, VDS=0.6 V
1
3
10
10
4
10
5
6
10
Frequency [Hz]
7
10
10
8
NMOS
PMOS
10
65 nm transistors W/L=600/0.10
@ ID=50 A, VDS=0.6 V
1
3
10
10
4
10
5
6
10
7
10
10
Frequency [Hz]
V. Re – in memoriam Franco Manfredi, Pavia, December 5, 2016
28
8

65 nm CMOS at extreme radiation levels
At the HL-LHC design luminosity, for an operational lifetime of 10 years, the
innermost pixel layer will be exposed to a total ionizing dose of 1 Grad, and to an
equivalent fluence of 1-MeV neutrons of 2 x 1016 n/cm2.
 If unacceptable degradation, a replacement strategy must be applied for inner
pixel layers.
 Nanoscale CMOS (with very thin gate oxide) has a large intrinsic degree of
tolerance to ionizing radiation: what happens at 1 Grad?

The RD53 Radiation
working group did an
excellent job in studying
and understanding
damabge mechanisms in
irradiated 65 nm CMOS
transistors
V. Re – in memoriam Franco Manfredi, Pavia, December 5, 2016
Radiation effects associated with STI oxides
TID induced
positive charge
TID induced
positive charge
STI
STI
Drain
Main transistor
finger
Gate
Lateral parasitic
devices
gate
P-type
Substrate
(Well)
P-type
substrate
tOX,lat,min
θ
STI
tOX,lat,max
Initially, with increasing dose a portion of the STI sidewall gets
inverted because of radiation induced positive charge trapped in
STI oxides. Lateral parasitic transistors are turned on and
contribute to the total noise of the device.
At higher doses, negative charge trapped at interface states
compensates positive oxide charge, and then may even become
dominant.
Lateral parasitic transistors are gradually switched off as TID
Source
30
V. Re – in memoriam Franco Manfredi, Pavia, December 5, 2016
increases further. Their noise contribution disappears.
Radiation effects associated with STI oxides
TID induced
positive charge
TID induced
positive charge
STI
gate
STI
Inverted region
at STI sidewall
Drain
Main transistor
finger
Gate
Lateral parasitic
devices
P-type
Substrate
(Well)
P-type
substrate
tOX,lat,min
θ
STI
tOX,lat,max
Inverted region
at STI sidewall
Initially, with increasing dose a portion of the STI sidewall gets
inverted because of radiation induced positive charge trapped in
STI oxides. Lateral parasitic transistors are turned on and
contribute to the total noise of the device.
At higher doses, negative charge trapped at interface states
compensates positive oxide charge, and then may even become
dominant.
Lateral parasitic transistors are gradually switched off as TID
Source
31
V. Re – in memoriam Franco Manfredi, Pavia, December 5, 2016
increases further. Their noise contribution disappears.
Radiation effects associated with STI oxides
TID induced
positive charge
TID induced
positive charge
STI
gate
STI
P-type
Substrate
(Well)
P-type
substrate
tOX,lat,min
θ
STI
tOX,lat,max
TID induced
Interface states,
negative charge trapping
Inverted region
at STI sidewall
Drain
Main transistor
finger
Gate
Lateral parasitic
devices
Inverted region
at STI sidewall
Initially, with increasing dose a portion of the STI sidewall gets
inverted because of radiation induced positive charge trapped in
STI oxides. Lateral parasitic transistors are turned on and
contribute to the total noise of the device.
At higher doses, negative charge trapped at interface states
compensates positive oxide charge, and then may even become
dominant.
Lateral parasitic transistors are gradually switched off as TID
Source
32
V. Re – in memoriam Franco Manfredi, Pavia, December 5, 2016
increases further. Their noise contribution disappears.
Radiation effects associated with STI oxides
TID induced
positive charge
TID induced
positive charge
STI
gate
STI
P-type
Substrate
(Well)
P-type
substrate
tOX,lat,min
θ
STI
tOX,lat,max
TID induced
Interface states,
negative charge trapping
Drain
Main transistor
finger
Gate
Lateral parasitic
devices
Initially, with increasing dose a portion of the STI sidewall gets
inverted because of radiation induced positive charge trapped in
STI oxides. Lateral parasitic transistors are turned on and
contribute to the total noise of the device.
At higher doses, negative charge trapped at interface states
compensates positive oxide charge, and then may even become
dominant.
Lateral parasitic transistors are gradually switched off as TID
Source
33
V. Re – in memoriam Franco Manfredi, Pavia, December 5, 2016
increases further. Their noise contribution disappears.
NMOSFETs – ID variation
No sizable effects can be seen in ID vs VGS static characteristics for devices with large
W/L, except in the leakage current region.
But looking at these data in more detail, it is possible to see interesting effects that
may be correlated with the behavior of noise in irradiated devices.
At low TID, positive charge in STI
oxides switches on lateral devices,
increasing ID (for the same VGS)
At higher doses, negative charge
trapped in interface states at the
STI oxides gradually compensates
oxide-trapped positive charge,
switching off lateral parasitic
transistors and reducing ID (for the
same VGS)
V. Re – in memoriam Franco Manfredi, Pavia, December 5, 2016
34
Total ionizing dose effects on noise in
LP 65 nm CMOS
• Noise is a crucial parameter for the performance of the analog front-end
(affects minimum threshold setting in particle tracking applications, single
photon resolution in X-ray imaging)
• The study of total dose effects on the noise of CMOS transistors can be
an effective tool to understand radiation damage mechanisms
• As an example, we developed a model for the contribution of lateral
parasitic transistors to the total noise of an irradiated NMOS
White noise
S
2
W , post
2
W ,pre
S
=
1/f noise
gm,main, pre
S
gm,main,post + gm,lat
S
2
1/ f ,post
2
1/ f , pre
A f ,lat æ gm,lat ö
» 1+
ç
÷
A f è gm ø
V. Re – in memoriam Franco Manfredi, Pavia, December 5, 2016
2
35
NMOSFETs
TSMC LP 65 nm technology – 10 Mrad
Low drain current density
High drain current density
Moderate 1/f noise increase at low current density, due to the contribution
of lateral parasitic devices
At higher currents the degradation is almost negligible because the impact of
the parasitic lateral devices on the overall drain current is smaller
No increase inV.the
noiseFranco
region
is detected
Re –white
in memoriam
Manfredi,
Pavia, December 5, 2016
36
NMOSFETs – up to 600 Mrad
Low current density
At high TID, the noise increase is not dependent on the current density, as it is
instead at 10 Mrad
At 200 Mrad (and even 600 Mrad), at low ID 1/f noise increase with respect to
pre-irradiation values is smaller than at 10 Mrad
This can be correlated with the evolution of radiation effects at increasing
Re – in memoriam
Manfredi, Pavia, December 5, 2016
TID and with the V.behavior
of ID Franco
vs VGS
37
NMOSFETs – 1/f noise coefficient
The effect of 1/f noise degradation
can be nonnegligible.
The dependence of 1/f noise
increase on the drain current density
is apparent at 10 Mrad.
At 600 Mrad, the 1/f noise
coefficient increases by about a
factor of 3.
At low ID, 1/f noise degradation is
more severe at 10 Mrad (increase
by almost a factor of 5) than at TID
beyond 100 Mrad
A possible explanation of this behavior is that at very high doses negative
charge trapped in interface states at the STI oxides gradually compensates
oxide-trapped positive charge, switching off lateral parasitic transistors
At high TID noise contributions by these parasitic devices become less important;
1/f noise increase from 200 Mrad to 600 Mrad can be explained by other effects
38
(increase of border
in gate
oxides,
defects
in spacer
dielectrics…)
V. Retraps
– in memoriam
Franco
Manfredi,
Pavia, December
5, 2016
1/f noise in irradiated PMOSFETs
Again no effect is detected in the white
noise region, while 1/f noise moderately
increases.
Lateral parasitic devices do not play a
role here (positive charge is accumulated
both in oxides and at interface states), so
there is no dependence on the drain
current density
1/f noise increase is smaller than in
NMOSFETs: at 600 Mrad the 1/f noise
coefficient increases by about a factor 2
(40% increase of the contribution to the
ENC of a detector readout channel)
V. Re – in memoriam Franco Manfredi, Pavia, December 5, 2016
39
Ionizing radiation effects on the signal-to-noise ratio
in a pixel readout channel
The noise data reported here can
provide the basis to estimate
the performance of an analog
front-end for pixel detectors
at extremely high TID
Noise voltage spectrum of NMOS,W/L = 5/0.13,
before irradiation and at 600 Mrad TID,
calculated using data from measurements
Even at a signal peaking time of 25
ns, radiation-induced 1/f noise
increase has an effect in the
bandwidth of an analog channel (input
transistor operates at very small ID,
in the low current density region)
Using realistic parameters for 65nm
CMOS pixel front-end prototypes
developed in the frame of RD53, a
15 - 20% ENC increase (from 120 to
140 e rms at 100 fF CD) can be
Transfer function of a shaperless front-end
predicted, which is consistent with
with 25 ns peaking time superimposed to the
40
V. Re
– in memoriam
Franco Manfredi, Pavia, December 5, 2016
measurements on
irradiated
chips
spectra
Ionizing radiation effects on the signal-to-noise ratio
in a pixel readout channel
400
C inj
I K /2
injection
enable
CK
recovery time
select
M3
i inj =Q d(t)
v out
to the discriminator
CD
CF
M1
M2
Peak value [mV]
The noise data reported here can
provide the basis to estimate
the performance of an analog
front-end for pixel detectors
at extremely high TID
V DD
test
input
300
200
gain select
detector cap
select
Even at a signal peaking time of 25
ns, radiation-induced 1/f noise
increase has an effect in the
bandwidth of an analog channel (input
transistor operates at very small ID,
in the low current density region)
V REF
100
IK
recovery time
select
0
Fig. 1. Schematic diagram of the charge preamplifier implemented in the
asynchronous front-end channel.
0
Fig. 2. Peak r
charge for the tw
from the charac
interval, or time-over-threshold. The preamplifier feedback
capacitor is discharged through a feedback network of the
Krummenacher type [4], which provides the CSA output advantages a
signal with a triangular shape. The triangular signal features of capacitor.
a relatively fast leading edge and a constant slope falling technology a
edge, resulting in a time to return to baseline proportional less susceptib
to the signal amplitude. As a consequence, the relationship the value of a
between the input charge and the ToT is very close to a given produc
linear one. The signal at the discriminator output is used as reduction can
a gate signal for the ToT clock (40 MHz), fed to a 5-bit, MIM module
dual-edge counter for time-to-digital conversion. The power
dissipation of the CSA is slightly in excess of 3.6 µW (about
3 µA at VD D =1.2 V). Its input device is an NMOS transistor
To test the
with W =5 µm and L =100 nm. The preamplifier has to be
D
samples wer
capable of processing signals in a range extending up to
Tandem acce
30000 electrons. As mentioned above, a few programming bits
INFN Labor
can be used to 5,
set the
charge sensitivity GQ (by changing the41
V. Re – in memoriam Franco Manfredi, Pavia, December
2016
divided in th
preamplifier feedback capacitance CF , which can be 10 or
Using realistic parameters for 65nm
CMOS pixel front-end prototypes
developed in the frame of RD53, a
15 - 20% ENC increase (from 120 to
140 e rms at 100 fF C ) can be
predicted, which is consistent with
measurements on irradiated chips
Conclusions
• During his scientific career Franco has oriented his
research interests to radiation detectors, detector
signal processing, noise limits in electron devices and
front-end electronics for different detector
applications.
• He has led several international projects in the area of
low-level, low-noise front-end systems for the
acquisition and processing of signals from radiation
detectors in nuclear and elementary particle physics
(CERN, IHEP, Fermilab, SLAC, LBNL,...)
• Most of his work was motivated by his belief that frontend electronics developments are among the main forces
responsible for the progress in physics
V. Re – in memoriam Franco Manfredi, Pavia, December 5, 2016
42
• Franco’s work is of central importance to the
field of detector readout electronics, and is
fundamental in understanding noise, detector
matching to front-end amplifier, signal shaping
and filtering, radiation effects in analog frontend circuits
• His work will always be an indispensable
reference for future developments of low-noise,
rad-hard readout electronics
• Franco’s work was essential for “disseminating
among the community “… a number of
instrumentation solutions that have been
developed with the aim of making
the…applications of solid-state detectors as
effective as possible” (E. Gatti, P.F. Manfredi,
La rivista del Nuovo Cimento 1986)
V. Re – in memoriam Franco Manfredi, Pavia, December 5, 2016
43
Backup slides
V. Re – in memoriam Franco Manfredi, Pavia, December 5, 2016
44
Programmable Gain
Preamplifier
Cf1
Programmable
Restorer
Cf
Bias
+
Gf
CD
CAC
-
Discriminator 0
Threshold
circuit
Shaper
CR-(RC)2
Baseline
BLR
Single-ended/
Differential
conversion
Comparator
Vth
+
Cinj
DAC
Test Input
Programmable
Peaking time
Discriminator 1
Threshold
circuit
Single-ended/
Differential
conversion
Comparator
Vth
+
DAC
Flash ADC
Discriminator 2
Threshold
circuit
Single-ended/
Differential
conversion
Comparator
Vth
+
DAC
V. Re – in memoriam Franco Manfredi, Pavia, December 5, 2016
FSSR2 block diagram
To silicon s trip de te ctors
1
16 se ts of logic e a ch
ha ndling 8 a na log cha nne ls
BCO ctr
Core Logic
Clock
P
rogra
mma
ble
DACs
Control
Re giste rs
Logic
P rogra mming Inte rfa ce
BCO clock
16
I/O
Word Se ria lize r
Ste e ring Logic
Re a dout
clock
V. Re – in memoriam Franco Manfredi, Pavia, December 5, 2016
Ne xt
Block
Word
High S pe e d
Output
Core
128 cha nne ls of a na log circuits
Data Output Interface
• FSSR2 Core
– 128 analog channels
– 16 sets of logic, each handling 8
channels
– Core logic with BCO counter
(time stamp)
• Programming Interface (slow
control)
– Programmable registers
– DACs
• Data Output Interface
– Communicates with core logic
– Formats data output
– Same as BTeV FPIX2 chip
Advanced pixel detectors and readout microelectronics
Particle tracking at LHC- Phase II:
• Very high hit rates (1-2 GHz/cm2), need of an intelligent pixel-level data
processing
• Very high radiation levels (1 Grad Total Ionizing Dose, 1016 neutrons/cm2)
• Small pixel cells to increase resolution and reduce occupancy (~50x50µm2
or 25x100 µm2)
 Large chips: > 2cm x 2cm, ½ - 1 Billion transistors
X-ray imaging at free electron laser facilities (next generation):
 Reduction of pixel size (100x100 m2 or even less), presently limited by the
need of complex electronic functions in the pixel cell:
 Large memory capacity to store images (at XFEL, ideally, 2700 frames
at 4.5 MHz every 100 ms)
 Advanced pixel-level processing (1 – 10000 photons dynamic range, 10-bit
ADC, 5 MHz operation)
V. Re – in memoriam Franco Manfredi, Pavia, December 5, 2016
47
RD53: an ATLAS-CMS-LCD collaboration
• RD53 was organized to tackle the extreme and diverse challenges associated
with the design of pixel readout chips for the innermost layers of particle
trackers at future high energy physics experiments (LHC – phase II upgrade
of ATLAS and CMS, CLIC)
65 nm CMOS is the candidate
technology to address the
requirements of these applications.
It has to be fully studied and qualified
in view of the design of these chips.
A 50 µm x 50 µm mixed-signal pixel cell
readout for the phase II upgrade of LHC in
65 nm CMOS
• ATLAS: CERN, Bonn, CPPM, LBNL, LPNHE Paris,
Milano, NIKHEF, New Mexico, Prague, RAL, UC
Santa Cruz.
• CMS: Bari, Bergamo-Pavia, CERN, Fermilab,
Padova, Perugia, Pisa, PSI, RAL, Sevilla, Torino.
– Collaborators: ~100, ~50% chip designers
V. Re – in memoriam Franco Manfredi, Pavia, December 5, 2016
48
RD53 chip architecture
•
•
•
95% digital (as for FEI4)
Charge digitization (TOT or ADC)
~256k pixel channels per chip
•
•
•
Pixel regions with buffering
Data compression in End Of Column
Chip size: >20 x 20 mm2
V. Re – in memoriam Franco Manfredi, Pavia, December 5, 2016
49
Specifications for threshold setting, noise, power, speed in
the ATLAS/CMS RD53 pixel analog front-end
Need of detecting charge released by MIPs in heavily damaged sensors
(4000 e-) at extreme irradiation levels without efficiency degradation
• Threshold setting for higher tolerable noise occupancy: Qth,min = 1000 e• ENC < 150 e rms at CD = 100 fF (mostly determined by series noise, ENC is
proportional to CD)
• Threshold dispersion after local tuning: sQth < 40 e rms
(includes contributions by discriminator threshold mismatch and
pixel-to-pixel preamplifier gain variations)
These specifications are based on the so called 4s rule (empirical):
Qth, min > 4.ENC + 4. sQth. They have to be achieved by analog circuits integrated
in a small silicon area and operating at very low power:
• Maximum power dissipation: 6 µW/pixel
(50 µm x 50 µm, or 25 µm x 100 µm)
V. Re –resolution
in memoriam Franco
Pavia,
December 5, 2016
• Maximum Hit time
= 25Manfredi,
ns, A/D
conversion
time < 400 ns
1/f noise in PMOS:
CMOS generations from 250 nm to 90 nm
1/2
Noise Voltage Spectrum [nV/Hz ]
1/f noise appears to increase (for a same WLCOX) with CMOS scaling
90 nm Foundry B W/L = 600/0.35
130 nm Foundry A W/L = 1000/0.35
250 nm Foundry C W/L = 2000/0.36
10
C = 5 pF
IN
PMOS
|V | = 0.6 V
1
DS
I = 500 A
D
10
3
10
4
10
5
10
6
10
7
10
8
Frequency [Hz]
V. Re – in memoriam Franco Manfredi, Pavia, December 5, 2016
51
NMOS and PMOS in an FD-SOI technology
We previously found that NMOS and PMOS have the same 1/f noise
only in one case, that is, in fully-depleted 180 nm CMOS SOI
transistors. A possible explanation was that in a very thin silicon film
(40 nm) conduction takes place very close to the Si-SiO2 interface.
NMOS
1/2
Noise Voltage Spectrum [nV/Hz ]
100
PMOS
10
FD-SOI CMOS devices
W/L = 100/0.5
I = 50 A
D
V
DS
1
10
3
= 0.6 V
10
4
10
5
10
6
10
7
Frequency [Hz]
V. Re – in memoriam Franco Manfredi, Pavia, December 5, 2016
52
1/f noise: NMOS vs PMOS
In bulk CMOS processes close to the 100 nm threshold, the PMOS
still has a lower 1/f noise than the NMOS. However, this difference
tends to decrease with newer CMOS generations.
100
PMOS
10
I = 500 A
D
1
180 nm NMOS Foundry A
W/L = 2000/0.2
3
10
10
4
10
5
Frequency [Hz]
180 nm
6
10
NMOS
1/2
Noise Voltage Spectrum [nV/Hz ]
NMOS
1/2
Noise Voltage Spectrum [nV/Hz ]
100
7
10
10
8
PMOS
10
I = 500 A
D
1
90 nm NMOS Foundry B
W/L = 600/0.35
3
10
10
4
10
5
6
10
7
10
10
Frequency [Hz]
90 nm
V. Re – in memoriam Franco Manfredi, Pavia, December 5, 2016
53
8
Thermal noise and CMOS scaling
The origin of thermal noise can be traced to the random thermal motion of
carriers in the device channel.
When the MOSFET is biased in saturation (VDS > VDS,sat), the following equation
can be used for the power spectral density of thermal noise in all inversion
conditions:
1
S  4 k BT
gm
2
W
   Wng
• kB = Boltzmann’s constant
• T = absolute temperature
 n  1
g mb
gm
(n = 1 – 1.5; proportional to the
inverse of the slope of the ID-VGS
curve in the subthreshold region)
• γ = channel thermal noise coefficient
(depends on inversion region; varies
with the inversion layer charge: =
1/2 in weak inversion, = 2/3 in
strong inversion)
• αw = excess noise coefficient
V. Re – in memoriam Franco Manfredi, Pavia, December 5, 2016
54
Excess thermal noise coefficient
1
S  4k BTng
W
gm
2
W
W = 1 for long-channel devices. Short-channel devices can be noisier
(W > 1 ) mainly because of two effects related to high longitudinal
electric fields (E = VDS/L) in the channel.
– Reduction of charge carrier mobility:
at increasing field strength the carrier velocity is
saturated at vsat=0EC (0 low-field mobility, EC
critical field strength)
– Increase of charge carrier temperature:
at increasing field strength the temperature Te
of carriers in the channel increases with respect
to the temperature T of the device lattice
V. Re – in memoriam Franco Manfredi, Pavia, December 5, 2016

0
E
1
EC
Te 
E 


 1 
T  EC 
55
b
Excess thermal noise coefficient
In saturation, the longitudinal electric field is E = (VGS – VTH)/L.
It can be shown that short-channel phenomena affect thermal noise only
if the value of the ratio E/EC is not negligible, which does not happen if
the device is biased in weak/moderate inversion.
350 nm CMOS
V. Re – in memoriam Franco Manfredi, Pavia, December 5, 2016
56
1/f noise from 350 nm to 65 nm NMOS
The 1/f noise parameter Kf does not show dramatic variations across
different CMOS generations and foundries in NMOS.
COX WLf
NMOS
f
• kf 1/f noise parameter
f
Kf
K
2 (f) 
S1/f
• αf 1/f noise slope-related
coefficient
-24
10
( 0.85 in NMOS,  1 – 1.1 in PMOS)
-25
10
350 nm 250 nm 180 nm 130 nm 90 nm 65 nm
Technology Node
V. Re – in memoriam Franco Manfredi, Pavia, December 5, 2016
57
White noise in 65 nm CMOS
Evaluated in terms of the equivalent channel thermal noise resistance:
R eq
S2W
ng

 W
4k B T
gm
• αw excess noise coefficient
• n proportional to ID(VGS) subthreshold characteristic
• γ channel thermal noise coeff.
800
[
Linear fit
offset = 4.75 +/- 7.71
slope = 1.09 +/- 0.03
500
Linear fit
offset = -7.85 +/- 8.92
slope = 1.04 +/- 0.03
700
600
Equivalent Noise Resistance
Equivalent Noise Resistance
[
600
400
300
200
NMOS
L > 65 nm
100
500
400
300
PMOS
L > 65 nm
200
100
0
0
0
100
200
300
400
500
600
ng/g [
m
0
100
200
300
400
500
600
700
800
ng/g [
m
w close to unity for NMOS and PMOS with L > 65 nm  no sizeable short channel effects
in the considered operating regions (except for 65 nm devices with w ≈1.3 )
Negligible contributions from parasitic resistances
V. Re – in memoriam Franco Manfredi, Pavia, December 5, 2016
White noise in 65 nm CMOS
V. Re – in memoriam Franco Manfredi, Pavia, December 5, 2016
59
The analog front-end
at extreme total ionizing dose
• Among other effects, PMOSFETs (especially minimum size ones) show a large
transconductance degradation, which becomes very steep over 100 Mrad (partial
recover after annealing)
• This is probably not so critical for the design of analog blocks, where minimum size
transistors can be avoided if necessary; the study of radiation effects on noise is
ongoing
• Damage mechanisms have yet to be fully understood; they appear to be less severe at
the foreseen operating temperature of the pixel detector at HL-LHC (about -15 °C)
CPPM data with X-rays
(Fermilab and Padova studying radiation
effects with other sources)
T = -15°C
T = -15°C
T = 25°C
T = 25°C
nmos : 120n/60n
V. Re – in memoriam Franco Manfredi, Pavia, December 5, 2016
pmos : 120n/60n
60
Total ionizing dose effects in NMOSFETs:
lateral leakage
In NMOSFETs edge effects due to radiation-induced positive
charge in the STI oxide generate sidewall leakage paths.
Shaneyfelt et al,
“Challenges in Hardening
Technologies using
Shallow-Trench Isolation”
IEEE TNS, Dec. 1998
Lateral
transistors have
the same gate
length as the
main MOSFET
L
NMOS finger
n
+
Drain
polyGate
Source
STI
Drain
Multifinger NMOS
Gate
Source
n+
Lateral parasitic
devices
Main transistor
finger
V. Re – in memoriam Franco Manfredi, Pavia, December 5, 2016
61
0 011110
00
SRAM
BUFFER
CF
Q .d
TOT
CASCADED
COUNTER BUFFERS
SHAPER
CD
PREAMPLIFIER
0
00
0 00 11110
00
0 11110 0
Block diagram of the front-end chip
for signal processing in the BaBar vertex detector
COMPARATOR
HIT
INFORMATION
BUILDING-UP
SPARSIFICATION
Vth
DATA
FORMATTING
V. Re – in memoriam Franco Manfredi, Pavia, December 5, 2016
DATA
TRANSMITTED