Transcript Loop-Level Parallelism and Thread

Chapter 3.4:
Loop-Level Parallelism and
Thread-Level Parallelism
• Software Approach to Exploits ILP
–Loop Unrolling and VLIW
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Thread Level Parallelism
Multithreading
Simultaneous Multithreading
Power 4 vs. Power 5
Head to Head: VLIW vs. Superscalar vs. SMT
Conclusion
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Loop Scheduling / Unrolling
• Textbook Section 3.2 (5th Edition)
• Source code (with x an array of doubles):
– for(I=1000;I>0;I--) x[I]=x[I]+s;
• Simple RISC assembly:
– Loop:
LD
ADDD
SD
SUBI
BNEZ
F0,0(R1)
F4,F0,F2
0(R1),F4
R1,R1,#8
R1,Loop
;F0=array el.
;add s in F2
;store result
;next pointer
;loop till I=0
• Latency:
–
–
–
–
FP ALU  FP ALU
3 cycles
FP ALU  Store Double
2 cycles
Load Double  FP ALU
1 cycle
Load Double  Store Double 0 cycle
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Stalls in Loop Execution
• Execution without scheduling:
(in-order pipeline)
Loop: LD
stall
ADDD
stall
stall
SD
SUBI
stall
BNEZ
stall
F0,0(R1)
F4,F0,F2
0(R1),F4
R1,R1,#8
! BNEZ need R1 2nd cycle
R1,Loop
Issued on cycle
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2
3
4
5
6
7
8
9
10
• 10 cycles per iteration!
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Example with Rescheduling
Reschedule instructions in the loop body:
Issued on cycle
Loop: LD
F0,0(R1)
1
SUBI R1,R1,#8
2
ADDD F4,F0,F2
3
stall
4
BNEZ R1,Loop
SD
8(R1),F4
Real work
Loop overhead
;delay branch 5
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Note: Loop execution time reduced by a factor of 6/10!
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Example with Loop Unrolling
Loop: LD
ADDD
SD
LD
ADDD
SD
LD
ADDD
SD
LD
ADDD
SD
SUBI
BNEZ
F0,0(R1)
F4,F0,F2
0(R1),F4
F6,-8(R1)
F8,F6,F2
-8(R1),F8
F10,-16(R1)
F12,F10,F2
-16(R1),F12
F14,-24(R1)
F16,F14,F2
-24(R1),F16
R1,R1,#32
R1,Loop
Note:
• 4-fold unroll; n-fold is possible.
• SUBI & BNEZ needed 1/4 as
often as previously.
• Multiple offsets used.
• Rescheduling has not yet been
done; still be a lot of stalls.
• But, use of different registers per
unrolled iteration will ease
subsequent rescheduling.
• Total 28 cycles: LD-2, ADDD-3,
SD-1, SUBI-2, BNEZ-2
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With Unrolling & Scheduling
Loop: LD
LD
LD
LD
ADDD
ADDD
ADDD
ADDD
SD
SD
SUBI
SD
BNEZ
SD
F0,0(R1)
F6,-8(R1)
F10,-16(R1)
F14,-24(R1)
F4,F0,F2
F8,F6,F2
F12,F10,F2
F16,F14,F2
0(R1),F4
-8(R1),F8
R1,R1,#32
16(R1),F12
R1,Loop
8(R1),F16
Note:
• LD/SD offsets depend on
whether instructions are above
or below SUBI.
• No stalls! Only 14 cycles per
iteration.
• 3.5 cycles per array element!
(10/3.5x faster than original)
• Note that the number of
overhead cycles per array
element went from 7 to ½!
• Would there be much speedup
from further unrolling?
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New Approach: Multithreaded Execution
• Multithreading: multiple threads to share the
functional units of 1 processor via overlapping
– processor must duplicate independent state of each thread
e.g., a separate copy of register file, a separate PC, and for
running independent programs, a separate page table
– memory shared through the virtual memory mechanisms,
which already support multiple processes
– HW for fast thread switch; much faster than full process
switch  100 to 1000 of clocks
• When switch?
– Alternate instruction per thread (fine grain)
– When a thread is stalled, perhaps for a cache miss, another
thread can be executed (coarse grain)
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Multithreaded Execution vs. CMP
• Multithreaded processor: multiple threads to share
the functional units of 1 processor via overlapping
thread execution
• CMP: has multiple cores (processors) and each
thread executed in a separate processor
• Key difference: majority of hardware are shared
among threads in multithreaded processor, while
CMP provides separate hardware for each thread
• The two can be combined by building CMP with
multithreading in each core
• Last-level (L2) cache is usually shared.
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Fine-Grained Multithreading
• Switches between threads on each instruction,
causing the execution of multiple threads to be
interleaved
• Usually done in a round-robin fashion, skipping any
stalled threads
• CPU must be able to switch threads every clock
• Advantage is it can hide both short and long stalls,
since instructions from other threads executed
when one thread stalls
• Disadvantage is it slows down execution of
individual threads, since a thread ready to execute
without stalls will be delayed by instructions from
other threads
• Used on Sun’s Niagara (will see later)
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Course-Grained Multithreading
• Switches threads only on costly stalls, such as L2
cache misses
• Advantages
– Relieves need to have very fast thread-switching
– Doesn’t slow down thread, since instructions from other
threads issued only when the thread encounters a costly
stall
• Disadvantage is hard to overcome throughput
losses from shorter stalls, due to pipeline start-up
costs
– Since CPU issues instructions from 1 thread, when a stall
occurs, the pipeline must be emptied or frozen
– New thread must fill pipeline before instructions can
complete
• Because of this start-up overhead, coarse-grained
multithreading is better for reducing penalty of
high cost stalls, where pipeline refill << stall time
• Used in IBM AS/400
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Do Both ILP and TLP?
• TLP and ILP exploit two different kinds of
parallel structure in a program
• Could a processor oriented at ILP to exploit
TLP?
– functional units are often idle in data path
designed for ILP because of either stalls or
dependences in the code
• Could the TLP be used as a source of
independent instructions that might keep
the processor busy during stalls?
• Could TLP be used to employ the functional
units that would otherwise lie idle when
insufficient ILP exists?
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Simultaneous Multi-Threading
One thread, 8 units
Cycle M M FX FX FP FP BR CC
Two threads, 8 units
Cycle M M FX FX FP FP BR CC
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1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
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9
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M = Load/Store, FX = Fixed Point, FP = Floating Point, BR = Branch, CC = Condition Codes
Simultaneous Multithreading (SMT)
• Simultaneous multithreading (SMT): insight that
dynamically scheduled processor already has many
HW mechanisms to support multithreading (section
3.12, 5th edition)
– Large set of virtual registers that can be used to hold the
register sets of independent threads
– Register renaming provides unique register identifiers, so
instructions from multiple threads can be mixed in
datapath without confusing sources and destinations
across threads
– Out-of-order completion allows the threads to execute out
of order, and get better utilization of the HW
• Just adding a per thread renaming table and
keeping separate PCs
– Independent commitment can be supported by logically
keeping a separate reorder buffer for each thread
– Fetch / Issue from multiple thread pre cycle
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Multi-issued / Multithreaded Categories
Fine-Grained Coarse-Grained
Multiprocessing
Time (processor cycle)
Superscalar
Simultaneous
Multithreading
Thread 1
Thread 2
Thread 3
Thread 4
Thread 5
Idle slot
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Design Challenges in SMT
• Since SMT makes sense only with fine-grained
implementation, impact of fine-grained scheduling
on single thread performance?
– A preferred thread approach sacrifices neither throughput
nor single-thread performance?
– Unfortunately, with a preferred thread, the processor is
likely to sacrifice throughput, when preferred thread stalls
• Larger register file to hold multiple contexts
• Not affecting clock cycle time, especially in
– Instruction issue - more candidate instructions need to be
considered
– Instruction completion - choosing which instructions to
commit may be challenging
• Ensuring that cache and TLB conflicts generated
by SMT do not degrade performance
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Power 5 with SMT
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Power 5 is Power 4 + SMT
Higher associativity of L1 I-cache and I-TLB
Add per-thread load and store queue
Bigger L2 and L3 caches
Separate instruction prefetch and buffering
Increase register file from 152 to 240
Increase issue queue size
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Initial Performance of SMT
• Pentium 4 Extreme SMT yields 1.01 speedup for
SPECint_rate benchmark and 1.07 for SPECfp_rate
– Pentium 4 is dual threaded SMT
– SPECRate requires that each SPEC benchmark be run
against a vendor-selected number of copies of the same
benchmark
• Running on Pentium 4 each of 26 SPEC
benchmarks paired with every other (262 runs)
speed-ups from 0.90 to 1.58; average was 1.20
• Power 5, 8 processor server 1.23 faster for
SPECint_rate with SMT, 1.16 faster for SPECfp_rate
• Power 5 running 2 copies of each app speedup
between 0.89 and 1.41
– Most gained some
– Fl.-Pt. apps had most cache conflicts and least gains
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ILP Competition
Processor
Micro architecture
Fetch /
Issue /
Execute
FU
Clock
Rate
(GHz)
Transis Power
-tors
Die
size
Intel
Pentium 4
Extreme
Speculative
dynamically scheduled;
deeply pipelined; SMT
3/3/4
7 int. 1
FP
3.8
125 M
122
mm2
115 W
AMD
Athlon 64
FX-57
Speculative
dynamically scheduled
3/3/4
6 int. 3
FP
2.8
114 M
115
mm2
104 W
IBM
Power5
(1 CPU
only)
Speculative
dynamically scheduled;
SMT;
2 CPU cores/chip
8/4/8
6 int. 2
FP
1.9
200 M
300
mm2
(est.)
80W
(est.)
Intel
Itanium 2
Statically scheduled
VLIW-style
6/5/11
9 int. 2
FP
1.6
592 M
423
mm2
130 W
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Performance on SPECint2000
Itanium 2
Pentium 4
AMD Athlon 64
Pow er 5
3500
3000
SPEC Ratio
2500
2000
15 0 0
10 0 0
500
0
gzip
vpr
gcc
mcf
craf t y
parser
eon
perlbmk
gap
vort ex
bzip2
t wolf
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Performance on SPECfp2000
14000
Itanium 2
Pentium 4
AMD Athlon 64
Power 5
12000
SPEC Ratio
10000
8000
6000
4000
2000
0
w upw ise
sw im
mgrid
applu
mesa
galgel
art
equake
facerec
ammp
lucas
fma3d
sixtrack
apsi
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Normalized Performance: Efficiency
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Itanium 2
Pentium 4
AMD Athlon 64
POWER 5
Rank
I
ta
ni
u
m
2
Pen
t
I
um
4
A
t
h
l
on
Po
we
r
5
Int/Trans
4
2
1
3
FP/Trans
4
2
1
3
Int/area
4
2
1
3
FP/area
4
2
1
3
Int/Watt
4 3
1
2
FP/Watt
2 4
3
1
30
25
20
15
10
5
0
SPECInt / M SPECFP / M
Transistors Transistors
SPECInt /
mm^2
SPECFP /
mm^2
SPECInt /
Watt
SPECFP /
Watt
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ILP Comparison
• No obvious over all leader in performance
• The AMD Athlon leads on SPECInt performance
followed by the Pentium 4, Itanium 2, and Power5
• Itanium 2 and Power5, which perform similarly on
SPECFP, clearly dominate the Athlon and
Pentium 4 on SPECFP
• Itanium 2 is the most inefficient processor both
for Fl. Pt. and integer code for all but one
efficiency measure (SPECFP/Watt)
• Athlon and Pentium 4 both make good use of
transistors and area in terms of efficiency,
• IBM Power5 is the most effective user of energy
on SPECFP and essentially tied on SPECINT
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Limits to ILP
• Doubling issue rates above today’s 3-6
instructions per clock, say to 6 to 12 instructions,
probably requires a processor to
– issue 3 or 4 data memory accesses per cycle,
– resolve 2 or 3 branches per cycle,
– rename and access more than 20 registers per cycle,
and
– fetch 12 to 24 instructions per cycle.
• The complexities of implementing these
capabilities is likely to mean sacrifices in the
maximum clock rate
– E.g, widest issue processor is the Itanium 2, but it also
has the slowest clock rate, despite the fact that it
consumes the most power!
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Commentary
• IA-64 architecture does not represent breakthrough
in scaling ILP or in avoiding problems of complexity
and power consumption
• Instead of pursuing more ILP, architects are more
focusing on TLP implemented with CMP
• In 2000, IBM announced the 1st commercial singlechip, general-purpose multiprocessor, the Power4,
with 2 Power3 and an integrated L2 cache
– Since then, Sun Microsystems, AMD, and Intel switch to a
focus on single-chip multiprocessors rather than more
aggressive uniprocessors.
• Right balance of ILP and TLP is unclear today
– Perhaps right choice for server market, which can exploit
more TLP, may differ from desktop, where single-thread
performance may continue to be a primary requirement
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Conclusion
• Limits to ILP (power efficiency, compilers,
dependencies …) seem to limit to 3 to 6 issues
Explicitly parallel (Data level parallelism or Thread
level parallelism) is next step to performance
• Coarse grain vs. Fine grained multihreading
– Only on big stall vs. every clock cycle
• Simultaneous Multithreading is fine grained
multithreading with OOO superscalar
microarchitecture
– Instead of replicating registers, reuse rename registers
• Itanium/EPIC/VLIW is not a breakthrough in ILP
• Balance of ILP and TLP decided in marketplace
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