Transcript 25 - Indico LAL

Habilitation à Diriger
des Recherches :
Calorimetry
from LHC to ILC
C. de La Taille
ATLAS calorimetry (1990)
• Challenging LHC
– High energy 14 TeV
– High collision rate : 40 MHz
– Small branching ratios…
• Challenging calorimetry
– Good resolution
– Small constant term (<1%)
– Low dead material
• Challenging electronics
–
–
–
–
Large dynamic range (16 bits)
Low noise
High speed
High radiation hardness
H -> ??
[F . Gianotti]
• Challenging schedule
– Be ready for 1999 !
25 sept 2009
100 fb-1
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2
ØT preamps
[NIM, PhD Y. Jacquier]
• Line terminating preamplifiers
–
–
–
–
Less radiation damage
No power inside LAr
No noise penalty at fast shaping
ENC ~ en/Z*tp
1  .RC C d tan .t d
Z
j.C d  j tan .t d / RC
• Current sensitive configuration
– Avoids saturation with large and
long LAr pulses
– Parallel noise negligible with fast
shaping
– Bipolar transistors, exhibit superior
series noise (en = 0.4 nV/√Hz)
25 sept 2009
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3
Shaping
[LArg10]
• Optimize signal to noise ratio
between electronics noise and pileup
noise
– High pass to clip long Lar tail
– Low pass to reduce series noise
– Optimum noise varies with luminosity
–
• Several notes on theoretical analysis
[LarG10, LArG 35]
– Current sensitive preamp : ENI
instead of ENC
– Pileup noise analysis
– Effect of preamp risetime
– Peaking time measurement tp 5%
– Alleviates 2nd stage noise issues
• ENI = A/tp3/2 + B/√tp
• Pileup : ENE = C√tp
25 sept 2009
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4
The LAr CRRC2 shaper [LArg 92]
• 4 channels tri-gain shaper
–
–
–
–
–
–
–
–
–
–
Gain ratio 1-10-100
Low noise (2 nV/√Hz)
High linearity (0.1%)
Low crosstalk (0.1%)
30 ns peaking time
Trimming with fuses to 1ns
High power (150 mW/channel)
AMS 1.2 µm BiCMOS technology
80 000 chips produced in 1998
Lots of irradiation tests !
DATE
mai-97
oct-97
juil-98
sept-98
juil-99
oct-99
nov-00
nov-00
25 sept 2009
Particle
N 6 MeV
g
60
g
60
Co
N
Co
60
g Co
P+ 20 MeV
N
60
g Co
Dose
2E13
2 kGy
1E14
2 kGy
2 kGy
2E13
2E13
3 kGy
rate
2 days
4 days
1 day
4 days
facility
SARA
Saclay
SARA
Saclay
2 months
2 days
2 days
2 days
Saclay
CERI
CERI
Saclay
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5
Digital filtering
[LArG 80, PhD Y. Jacquier]
• Multiple Sampling technique
[Cleland 1996]
Sampled signal shape
– Linear combination of 5 samples on
waveform to optimize noise
– Finite Impulse Filter
• Signal : s(t)=Ag(t)+b
–
–
–
–
A : amplitude
G(t) : normalised signal shape
B : noise
Sampled signal : si=Agi+bi
Autocorrelation function
• Filter : weighted sum Σ ai si
– ai = Σ R-1ij gi
– R = autocorrelation fonction
– gi = signal shape
(0, 0.63, 1, 0.8, 0.47)
– S = Σ aisi
25 sept 2009
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Digital Filtering (2)
• Slowing down the signal
A = (0.17, 0.34, 0.4, 0.31, 0.28)
– Reduction of series noise
– Similar to a simple integration
[ATLAS-LArG-080]
• Accelererating the signal
– Reduction of pileup noise
– Similar to a differentiation
• Measuring the timing
A = (-0.75, 0.47, 0.75, 0.07, -0.19)
• Several questions [PhD Jacquier]
– How does-it compare to an analog
filter ?
– How many samples are needed ?
– What accuracy is needed on the
waveform and on the
autocorrelation ?
– What analog shaping time is
needed ?
– Is the analog filter really useful ?
25 sept 2009
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2m prototype (1994)
• Moving to large scale : 2 m
• Good results : 1% @ 200 GeV
• Pending issues
–
–
–
–
preamps choice
Feedthroughs
Large dimension electrodes
Cables, connectics…
25 sept 2009
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Time of TDR (1996)
• Detector defined
– 3 samplings in depth
– Granularity : 0.025x0.025
– Kapton cables for readout
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Time of TDR (1996)
• Readout chain defined
–
–
–
–
–
–
0T preamps
Trigain shaper
Analog memories
DMILL custom chips
12 bit 5 MHz ADC
Optical output
• On detector electronics
–
–
–
–
–
Calibration
Front-End boards
Tower builder
Controller
Power supplies
Harness ‘A’
25 sept 2009
Pigtail ‘B’
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Vacuum ‘C’
Warm cable ‘D’
10
Calibration
[NIM]
• Generate 0.1% accuracy pulse over
16 bits dynamic range
ROOM T
LAr
– Inject with 0.1% accuracy resistor
– Fabricate fast accurate pulse 50 µV
to 5 V, tr ~1 ns, td ~400 ns
– Operate in magnetic field ~100Gauss
– Tolerate radiations
• Uniformity < 0.25%
0.1%
Rinj
25 sept 2009
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11
History
• 12 boards produced in 1998 with COTS for
module 0
– 5 years successful operation in beam tests.
– Excellent uniformity : 0.11% rms on 1300 channels
– But radiation soft : COTS failed at 20 Gy
• Active elements designed in DMILL in 1999-2001
– DAC, Pulser, Control logic, delay chip
– Radiation qualified at 5 kGy
– Improved performance (DAC stability, parasitic
signal at DAC=0, DAC stability and offset)
– Simplified logic, 10 Alteras replaced by 6 identical
ASICs (DMILL Calogic)
– All ASICs produced in 2003 (30 000 opamps)
• First final boards produced in 2002-2003
– Final design review in 2002
– Production readiness review passed in march 2004
– Production of 140 boards in 2004-2005
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Uniformity of Calib0
12
Calibration board overview
•
•
•
•
A 16 bit DAC voltage is distributed to the 128 channels.
One low offset op.amp. per channel generates the calibration current ICAL
through a 5Ω [0.1%] external precision resistor.
The current source is radiation tolerant up to 2 kGy and 2.1013 N/cm2
The pulse is made by interrupting ICAL with a high frequency switch
RTCTID
VP5 reference point
5W
0.1%
25 µV
?V
50 W
0.1%
16 bits R-2R
DAC
Vmax = 1V
LSB = 15 µV
25 sept 2009
RTCNIEL
Death of
mux
readout
25 µV
?V
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Final calibration board layout
128 Opamps
& switch
Calogic
Outputs
CH0-63
VP5
«star point»
DCU
DAC
TTCRx
Outputs
CH64-127
Delay
(bottom)
SPAC3
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Pulse shape before shaping
• Full DAC range
– 100 µV  1V
– Up to 5V pulses in 50Ω
Pulse output without shaping
• Rise time < 2 ns
– Small increase at large DAC
• Decay time ~ 450 ns
– Matched to Argon drift time
– Accuracy :  2%
• HF Ringings :
– At small DAC values, due to
parasitic package inductance in
HF switch
– « Parasitic injected charge »
– 20 mV pk-pk
– Very small area
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Pulse shape after shaping
• Parasitic injected charge (PIC)
– Peak of Qinj : equivalent to
DAC=30 µV (2LSB)
– At signal peak :
PIC < DAC = 15 µV = 1 LSB
Pulse output after 50 ns shaping
(~30 MeV in Barrel Middle < noise)
– Improvement by >10 compared
to module 0
• CMD feedthrough
– Parasitic pulse on disabled
channels
– Equivalent to DAC=3 µV =0.2
LSB : ~negligible
3
=
2
1
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pulse uniformity and linearity
• Linearity : < 0.1%
–
–
–
–
Red : at signal peak
Black : peak of signal
Dominated by readout non-linearity
DC linearity < 0.01%
pulse linearity vs DAC
• Uniformity at DAC=5000
– Rms : 0.13%
(DC was 0.07%)
– Additionnal contribution from output
resistors, output lines, inductors and
scanner board
pulse
uniformity
rms
0.13%
25 sept 2009
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Production problems
• 140 boards produced
– Extensive analog tests
– Non uniformity seen after burn-in
– Traced to cracks in vias during
assembly
– Very small resistance increase <1Ω
– Degrades with time => open
– PCB redone with better FR4
• Excellent performance
– Uniformity : 0.5%
– Offset 15 µV rms
25 sept 2009
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Calibration sensitivity to cables
• Sensitivity to cable characteristic
impedance Zc
Amplitude vs cable impedance
– Second order effect (if terminated both
ends) : dV/V = 1 – (dZc/2Zc)2
– ± 2.5Ω on cable gives ± 0.1%
- 0.1%
• Sensitivity to skin effect
– First order effect :
± 5%
• - 1.2 %/m @ 300 K,
• - 0.5 %/m @ 77 K
– Correction necessary for cable length
– Calibration cable length : 3-6 m : expect ~
0.2% contribution at cold (~0.4% at
warm)
25 sept 2009
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Amplitude vs cable length
19
Calibration at cable output
50Ω coax
l=1-5m
50Ω coax
l=1m
35Ω stripline
l=0.3m
35Ω stripline
l=0.3m
Feedthrough
Calibration pulse at cable output
pulse uniformity at cable output
T=300K
T=300K
rms
0.44%
Feedthrough reflection
25 sept 2009
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Difference between calibration and physics
• Calibration pulse shape
– Exponential shape vs triangle
– Systematic effect in tSHAPER/tCAL
– Accuracy in calib decay time tCAL: ± 2%
• Detector inductance
– Physics signal at shower max in the middle
of the accordion : non negligible output line
: inductive effect
– Sizeable effect : - 0.2%/nH on
physics/calibration ratio
– Inductance measurement necessary
Physics signal
Calibration pulse
25 sept 2009
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ATLAS Lar : detector modelization
• Line model
Absorber
– “stripline” Absorber-LAr-HV-KaptonSignal. Propagation td = 4.12 ns/m
– Solving Poisson to calculate
capacitances Cd, Cx and impedance
: Zc = td/Ct
LAr
HV el.
• Good lumped model
– Detector (Zc = 1.5-2Ω )
= capacitance (1 - 1.5nF)
– Connection (Zc = 15-20Ω )
= inductance (20-30 nH)
25 sept 2009
Signal electrode
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Neighbor
22
Detector measurement
• Scan of the 60 000 Middle channels
– 3 points measurement
– Resonant frequency unaffected by
cables
– 1% measurement accuracy
• Used in database to correct
calibration bias
25 sept 2009
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Crosstalk and γ/π0 rejection [LArG 31]
• Large crosstalk in front strips (8%)
–
–
–
–
Cx ≈ Cd + fast shaping
Can deteriorate γ/π0 rejection
Signal broadening
Noise correlations
• Analtyical calculations
– Crosstalk capacitance
– Crosstalk signals & noise correlation
– Feeds Geant 3 for γ/π0 simulation
25 sept 2009
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Crosstalk task force
[LArG 00-06]
• Some large crosstalk (2-5%)
– Task force formed
• Many unusual sources
– Inductive loops
– Ground resistance
– Ground apertures
• Actions taken
– Redesign of motherboards,
summing boards, connectors
– Gold plating of feedthroughs
25 sept 2009
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Module 0 tests and results
9.2 % /E0.3 %
25 sept 2009
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ATLAS ready for data taking (2007)
25 sept 2009
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« Imaging calorimetry » at ILC
• Particle flow algorithm
–
–
–
–
–
–
Reconstruct each particle individually
Bring jet resolution down to 30%/√E
Measure charged particles in tracker
Measure photons in ECAL
Measure hadrons in ECAL and HCAL
Minimize confusion term
• Calorimeter design
–
–
–
–
–
High granularity : typ < 1 cm2
High segmentation : ~30 layers
Moderate energy resolution (10%/√E)
ECAL : Silicon-Tungsten
HCAL : analog vs digital
©J.C Brient (LLR)
F. Sefkow (DESY)
• CALICE collaboration
– « a high granularity calorimeter optimized
for particle flow algorithm »
– 280 phys./eng., 11 countries, 42 labs
25 sept 2009
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ILC Challenges for electronics
• Requirements for electronics
–
–
–
–
Large dynamic range (15 bits)
Auto-trigger on ½ MIP
ASIC
On chip zero suppress
Front-end embedded in detector Si pads
– Ultra-low power : ( « 25µW/ch)
– 108 channels
Ultra-low
– Compactness
•
POWER
W layer
« Tracker electronics with calorimetric
is the
performance »
KEY issue
• No chip => no detector !!
ILC : 25µW/ch
25 sept 2009
FLC_PHY3 18ch 10*10mm 5mW/ch
ATLAS LAr FEB 128ch 400*500mm 1 W/ch
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CALICE prototypes
• 1 m3 physics prototype
– Goal : study particle flow
algorithm
– Validate simulation and check
performance of detectors in TB
• 4 calorimeters in testbeam
(since 2003)
–
–
–
–
–
ECAL : W-Si 24X0 20x20 cm2
AHCAL : Tiles + fibers + SiPMs
DHCAL : RPCs
Already 104 to 4 105 channels !
Run at DESY (05), CERN (06),
FNAL (07 and 08)
• Moving to large scale (1.5m)
technological prototypes :
« 2nd generation ASICs and DAQ»
– European funding « EUDET »
– HaRDROC, SKIROC, SPIROC…
25 sept 2009
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CALICE ECAL Physics Prototype Overview
• 30 layers of variable thickness Tungsten
• Active silicon layers interleaved
• Front end chip and readout on PCB board
• Analog signals sent to DAQ
• 10,000 channels
•PCB contains VFE electronics
•14 layers, 2.1mm thick
•Analogue signals sent to DAQ
© M. Anduze
360mm
360mm
•6x6 1x1cm2 silicon pads
•Connected to PCB with
conductive glue
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62 mm
31
FLCPHY3 front-end ASIC
• Low noise charge preamp
–
–
–
–
1 channel
optimized for Cd=70pF.
Noise en=1.6 nV/
ENC = 1000e- + 40 e-/pF
Variable gain (Cf = 0.2 -> 3 pF)
OPA
G10
OPA
G1
• Dual gain shaper (G1-G10)
– Shaping time tp = 200 ns
– dynamic range : 500 MIPs (G1, Cf=1.6
– Noise : 0.1 MIP (G1)
Amp
• 2000 chips produced in 2003
Synoptic of 1 channel of FLCPHY3
Output waveforms for various PA gain
Measured gain vs set gain
25 sept 2009
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Performance of physics prototype
• 3 years of successful data taking
– MIP/noise ~8
– Energy resolution 16%/√E
25 sept 2009
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Technological prototypes : “EUDET module”
• Front-end ASICs embedded in detector
– Very high level of integration
– Ultra-low power with pulsed mode
– Target « analog friendly » SiGe technology
• All communications via edge
– 4,000 ch/slab, minimal room, access, power
– small data volume (~ few 100 kbyte/s/slab)
– « stitchable » motherboards 18x18 cm
• EUDET funding for fab in 2009
25 sept 2009
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ECAL detector slab
•
•
•
•
Chips bonded on board (ASU) : yield issues
No external components : EMC/EMI issues
Minimize inter-connections : reliability issues
Embedded electronics : thermal issues
Connection between 2 A.S.U.
Chip embedded
Short sample
25 sept 2009
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Read out: token ring
• Readout architecture common to all calorimeters
• Minimize data lines & power
ILC beam
Chip 0
Chip 1
Chip 2
Chip 3
Chip 4
Data bus
Chip 0
Acquisition
A/D conv.
Chip 1
Acquisition
A/D conv.
IDLE
Chip 2
Acquisition
A/D conv.
IDLE
IDLE MODE
Chip 3
Acquisition
A/D conv.
IDLE
IDLE MODE
Chip 4
Acquisition
A/D conv.
IDLE
.5ms (.25%)
.5ms (.25%)
1ms (.5%)
DAQ
1% duty cycle
25 sept 2009
IDLE MODE
DAQ
IDLE MODE
DAQ
IDLE MODE
199ms (99%)
99% duty cycle
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Second generation ASICs
• Add auto-trigger, analog storage,
digitization and token-ring readout !!!
• Include power pulsing : <1 % duty cycle
• Address integration issues asap
• Optimize commonalities within CALICE
(readout, DAQ…)
HARDROC
Digital HCAL
(RPC, µmegas)
64 ch. 16mm²
FLC_PHY3
(2003)
25 sept 2009
Sept 06
SKIROC
ECAL
(Si PIN diode)
36 ch. 20mm²
SPIROC
Analog HCAL
(SiPM)
36 ch. 32mm²
Nov 06
June 07
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HARDROC: HAdronic Rpc Digital ReadOut Chip
• Variable gain (6bits) current
preamps (50Ω input)
• Auto-trigger on ½ MIP
• Store all channels and BCID for
every hit. Depth = 128 bits
• Data format :
128(depth)*[2bit*64ch+24bit(BCID)+
8bit(Header)] = 20kbits
• Power dissipation : 1.5 mW/ch
(unpulsed)-> 7 µW with 0.5% cycle
• Large flexibility : >500 slow control
•
settings
SiGe 0.35µm sept 06 and june 08
25 sept 2009
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HaRDROC preamplifier
• Current conveyor
– « Super common base » configuration
– low input impedance, small « equivalent
inductance » (<20 nH)
– Zin = 1/gm1gm2Rc = 50-100Ω
– good performance of SiGe
• Variable output mirrors : 8 bits
– Gain accuracy : 1%
f=300MHz
f=6GHZ
25 sept 2009
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Power pulsing
• Total power on : 100 mW
• Total power off : 10 µW
• Power dissipation
PWR ON
– 1.5 mW/ch continuous
– 25 µs awake time
– 7.5 µW/ch with 0.5% duty cycle
• 10 µW/ch = 24h operation of full slab
with 2 AAA batteries !
PA
5.46mA
DAC
0.84mA
3 FSB
12.3mA
BG
1.2mA
SS
9.3mA
vddd
0.67mA
3 Discris
7.3mA
vddd2
0.4mA
25 µs
Trigger
(=0 if 40MHz
OFF)
TOTAL
25 sept 2009
38mA
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Analog and Digital crosstalk
• Analog Crosstalk ~1%
– Well differentiated, capacitive like
– Dominated by the input
– No long distance crosstalk
• Digital crosstalk : 3 fC
– Coupling of discriminator to inputs through
ground or substrate
– Trigger on CH1 and look at analog
signal on CH2
NO decoupling cap.
25 sept 2009
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Trigger efficiency measurements
After Gain ccorrection
50% point
50% point
± 25fC
± 5fC
Dac unit
High gain : DAC Unit ≈ 1 fC
Low gain : DAC Unit ≈ 3 fC
1pC
30 fC
10 fC
100 fC
Pedestal
FSB0, 100K, 100fF, G=144
Channel number
25 sept 2009
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piedestal
42
HARDROC1: digital part
25 sept 2009
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TESTBEAM (CERN, 2008):
1st
GRPC
2d
GRPC
3d
GRPC
Hit
pads
4th
GRPC
5thGRP
C
@I.Laktineh-IPNL
44
25 sept 2009
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TOWARDS A TECHNOLOGICAL PROTOTYPE
Slab #1
GRPC
Slab #2
Slab #3
Fully equipped large scalable detector to be soon
tested in cosmic rays bench and in test beam at
cern in summer 09
25 sept 2009
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DIF #1
DIF #2
DIF #3
45
AHCAL: Technological prototype
•
SiPM detector: 40 layers of 1.5 m2 2 cm
thick steel plates interleaved with
cassettes of 296 scintillating tiles (3x3
cm2) readout by SiPMs
•
FE Chip embedded inside the detector
– Thickness:critical issue: Mother boards
(HBU) are sandwiched between 2
absorber plates
Mephy SiPM
25 sept 2009
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SPIROC: Silicon Photomultiplier Integrated Read Out Chip
• A-HCAL read out
–
–
–
–
–
Silicon PM detector G=105-106
36 channels
Charge measurement (15bits)
Time measurement (< 1ns)
many SKIROC, HARDROC, and
MAROC features re-used
– Submitted in June 07 in SiGe 0.35
µm AMS
SPIROC
• Collaboration with DESY
– Physics prototype: 9000 channels
used in test beam in 2004-2008
– Production in 2009 for Eudet
module (technological prototype)
25 sept 2009
FLC_SiPM
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SPIROC main features
• Internal input 8-bit DAC (0-5V) for individual SiPM gain adjustment
• Energy measurement : 14 bits
– 2 gains (1-10) + 12 bit ADC: 1 pe  2000 pe
– Variable shaping time from 50ns to 100ns
– pe/noise ratio : 11
• Auto-trigger on 1/3 pe (50 fC)
– pe/noise ratio on trigger channel : 24
– Fast shaper : ~10 ns
– Auto-Trigger on ½ pe
• Time measurement :
– 12-bit Bunch Crossing ID
– 12 bit TDC step~100 ps
•
•
•
•
•
•
•
Analog memory for time and charge measurement : depth = 16
Low consumption : ~25 µW per channel (in power pulsing mode)
Individually addressable calibration injection capacitance
Embedded bandgap for voltage references
Embedded 10 bit DAC for trigger threshold and gain selection
Multiplexed analog output for physics prototype DAQ
4k internal memory and Daisy chain readout
25 sept 2009
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SPIROC : One channel schematic
0.1pF-1.5pF
1.5pF
Low gain
Preamplifier
0.1pF-1.5pF
15pF
Slow Shaper
Analog memory
50 -100ns
Depth 16
High gain
Preamplifier
Charge
measurement
Depth 16
15ns
Discri
Common to the
36 channels
25 sept 2009
ADC
Conversion
Variable delay
80 µs
Trigger
Depth 16
DAC output
12-bit
Wilkinson
READ
HOLD
Fast Shaper
8-bit DAC
0-5V
Gain
Slow Shaper
50-100ns
IN
Gain
selection
Flag
TDC
4-bit threshold
adjustment
10-bit DAC
TDC ramp
Time
measurement
300ns/5 µs
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ValidHoldAnalogb
16
RazRangN
16
Chipsat
16
ReadMesureb
Acquisition
ExtSigmaTM (OR36)
gain
Wilkinson ADC
Discri output
StartAcqt
SlowClock
Hit channel register 16 x 36 x 1 bits
TM (Discri trigger)
Trigger discri Output
36
BCID 16 x 8 bits
Channel 0
gain
36
ValGain (low gain or
high Gain)
Conversion
ADC
EndRamp (Discri ADC
Wilkinson)
Trigger discri Output
StartConvDAQb
TransmitOn
readout
+
36
Wilkinson ADC
Discri output
NoTrig
FlagTDC
RamFull
OutSerie
EndReadOut
Ecriture
RAM
StartReadOut
Rstb
Channel 1
Clk40MHz
..…
…
TDC ramp
ADC ramp
Startrampb
(wilkinson
ramp)
OR36
StartRampTDC
Chip ID register 8 bits
RAM
ChipID
8
ValDimGray
ASIC
25 sept 2009
ValDimGray 12 bits
12
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DAQ
50
SPIROC layout
8x4= 32mm2
36
8bit
5V DAC
Bandgap
25 sept 2009
36
Preamp
Shaper
discri
36*16
Analog
memory
36*2
Wilkinson
ADC
SRAM
Readout
Dual DAC
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Performance
©Beni (DESY)
©W.Shen (Heidelberg)
High gain channel
linearity
Linearity better than
1%
pedestal
25 sept 2009
Qinj=50fC
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Internal 12-bit ADC performance
Chip 1
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Time measurement
• ~1 ns requirement for delayed neutrons tagging
• ~100 ps for medical applications
• Time to Amplitude converter using Wilkinson ADC
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Multi-Anode PM readout : OPERA_ROC
[NIM]
• OPERA_ROC : 32 ch ASIC
– Variable gain preamp
– Autotrigger on 1/3
photoelecton
– Multiplexed charge readout
– BiCMOS 0.8µm 3000 chips
produced (2002)
64 ch front-end board (BERN)
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MAROC : MultiAnode Read-Out Chip
[NIM]
• Complete front-end chip for 64 channels
multi-anode photomultipliers
–
–
–
–
6bit-individual gain correction
Auto-trigger on 1/3 p.e. at 10 MHz
12 bit charge output
SiGe 0.35 µm, 12 mm2, Pd = 5 mW/ch
• Bonded on a compact PCB (PMF) for
ATLAS luminometer (ALFA)
• Also equips Double-Chooz, medical
imaging…
Hold signal
64 inputs
Photons
PM
64 channels
Gain
correction
64*6bits
3 discris
thresholds
(3*12 bits)
25 sept 2009
Variable
Gain
Preamp
.
Variable
S&H
Slow
Shaper
S&H
64
20-100 ns
Bipolar
Wilkinson
Fast Shaper
12 bit ADC
Unipolar
80 MHz
encoder
PMF
Fast Shaper
3 DACs
12 bits
Multiplexed
Analog charge
output
Multiplexed
Digital charge
output
64 trigger outputs
(to FPGA)
LUCI
D
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PARiSROC for PMm2
•
[PhD S. Conforti]
“PMm2” (2006 – 2009), funded by
the ANR : LAL, IPNO, LAPP, Photonis
–
Joël PouthasIPN Orsay
Replace large PMTs (20”) by groups of
smaller ones (12”)
– central 16ch ASIC (PaRISROC)
–
–
–
–
12 bit charge + 12 bit time
water-tight, common High Voltage
Only one wire out (DATA + VCC)
Target low cost
•
Application : large water Cerenkov
neutrino
•
External requests :
–
Neutrino (DUSEL, LENA)
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PARISROC1 performance
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PARISROC1 performance
©B Genolini (IPNO)
Threshold = 220 DAC
channels
©B Genolini (IPNO)
0.3
pe
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Conclusion
• Importance of close interaction between physics and front-end
• High level integration thanks to micro-electronics technology
• Large synergy between chips : efficiency of micro-electronics poles
« acta est fabula »
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Conclusion (2)
• Thanks to all the OMEGA team !
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Semiconductor Industry Roadmap
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Spare slides
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backup slides
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Effect of radiations on components
• TID : total ionising dose effects
Radiation levels in ATLAS (rads/an)
– Charge trapping in gate oxide
R (m)
– Alleviated in thin oxides (Deep
FEC
SubMicron DSM)
FEC
1 krad/an 1011 N/cm2
– Radiation tolerant layout
techniques designed by CERN RD49
in 0.25µm
• NIEL : non ionising energy loss
– Cristal damage with neutrons
– Beta drop in bipolar transistors
1 Mrad/an 1014 N/cm2
Z (m)
• SEU : Single Event Effect
– Effect of large ionising impact :
local charge deposition on critical
nodes
– SEU : single event Upset = bit flip
– SEL : single Event Latchup :
thyristor setting -> destructive !
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DC performance
DC linearity < 0.01%
25 sept 2009
DC uniformity 128ch 0.06%
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Calibration performance
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Towards ECAL DAQ : data volume and rate
• Raw Data volume
– 2 bytes Energy data/Channel, 20 Million channels
– Raw data per bunch train ~ 20M  5000  2 ~ 200GBytes
ECAL
– No way to digitize inside the ~ ms train
– 10 kbytes/channel/train ~ 50 kbytes/ch/s
– Physics data rate : 90 Mbytes/train = ~20 bytes/ch/s
• Zero suppression mandatory
– 103 rate reduction -> drastic for power dissipation
– Digitize only signals over 1/2MIP with noise < MIP/10
– Allow storage in front-end ASIC
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EUDET module FEE : main issues
• “stictchable” motherboards
– Minimize connections between boards
• No external components
– Reduce PCB thickness to <800µm
– Internal supplies decoupling
• Mixed signal issues
– Digital activity with sensistive analog
front-end
“EUDET ECAL module
• Pulsed power issues
–
–
–
–
Electronics stability
Thermal effects
To be tested in beam a.s.a.p
.
• Low cost and industrialization are the
major goal
Slab exploded view
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CALICE AHCAL testbeam prototype
• Hadronic calorimeter prototype for the ILC : 1 cubic metre, 38 layers,
2cm steel plates
• 8000 tiles with SiPMs fabricated by MePHY group
FLC_SiPM
ASIC
Mephy SiPM
Mechanics and front end boards: DESY
Front end ASICs: LAL
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W/Sci SiPM
japanese ECAL
with MPPCs
71
SiPM readout aSIC : FLC_SiPM
• FLC_SiPM readout ASIC
– 18 channel variable gain preamp and
shaper
– Dynamic range : 13 bits (2 gains)
– 8 bit DAC/channel for SiPM gain
adjustment
– 1000 chips produced in 2004
 Power consumption :
~200mW (supply : 0-5V)
 Technology : AMS 0.8 m
CMOS
 Chip area : ~10mm²
 Package : QFP-100
Single photoelectron spectrum © E. Popova
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Input DAC
8 bit, 5V range
5
LSB=20mV
4,5
36 DACs : one per channel
4
Ultra low power (1µW) : no power3,5
3
pulsing
2,5
• Can sink 10 µA leakage current
2
1,5
• Linearity : ± 2%
DAC linearity
Voltage (V)
•
•
•
•
1
0,5
+HV
0
0
8-bit
DAC
50
100
150
200
250
300
DAC
0,03
0,02
Si
PM
0,01
0
-0,01
High
voltage
on the
cable
shielding
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-0,02
ASIC
-0,03
-0,04
0
50
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100
150
200
250
300
73