Transcript 2000

Process technology
Physical layout with L-Edit
T. Delbruck
Neuromorphic Engineering 2
Lecture 2
Analog Chip CAD design tools
Design
Verification
S-Edit
T-Spice
Schematic editor
L-Edit
Layout editor
DRC
Design rule checker
Circuit simulator
LVS
Layout vs. Schematic
Extract
Netlist extractor
Mask layout
L-Edit
1947
~1950
Bardeen and Brattain
2000
~2000
A finished wafer
Superficial historical timeline of fabrication technology development
1930
Lilienfield patents on field-effect transistors
1940
Ohl Silicon PN junction
1950
Bell labs, Bardeen Brattain make point contact bipolar
bipolar
Phillbrick tube opamp
1960 30u
1970 10u
1980
1990
2000
2010
Fairchild founded
Accutron watch
Kilby/TI integrated circuit, Noyce/Fairchild planar process
63 Widlar/National uA701 opamp
Intel founded ($34B sales 2004)
Faggin silicon gate ‘73 Intel 8008 DEC PDP-11
nMOS
‘74 National LM324 opamp
‘78 Intel 8086
1u
0.25u
90nm
50nm?
CMOS
TSMC fab founded ($6B sales 2003)
IBM’s CMP planarization enables many metal levels
Motorola PowerPC 601
NTRS Roadmap
Cost of chip production
• At 1000 wafers/month (lots of parts!)
– ~$600/6 inch 0.25u wafer=~$3.50/cm2
– Add for packaging ~0.25 cents/pin for QFP
(about most expensive)
– Add for testing $200/hour for 256 pin mixed
signal tester; about 1 second to move sites
• (6 inch wafer ~ 180 cm2, 8 inch ~ 310 cm2)
From numbers like these, you can compute
production price of your chip
Thanks to Chuck Neugebauer for prices ca. 2006
Moore’s “law” (more like observation)
• Number of
transistors per
chip doubles
every 1.5 to 2
years
• Cost/bit drops
29%/year
• True for last 45
years!
0.25u
2000
90-65nm
Tobi’s extrapolation
N-Select
(implant)
Inverter layout
Contact
N-well
Metal1
Poly
Via
Metal2
P-Select
(NOT
N-select)
Active
(thin oxide)
G
S
n+
p+
holes
G
D
S
p+
electrons
n+
n well
p--- epi
p+ wafer
p well
D
n+
p+
CMOS process technology
• A wafer is photolithograpically processed
using a set of masks
• A typical process has ~15-40 masks
• Each mask patterns a layer
• The exact process steps vary, but a single
photolithographic step uses a common
technology for patterning
What can a process do?
• Pattern
– Photolithography exposes photoresist to removes it selectively
• Deposit
– Use chemical vapor deposition (CVD) to coat wafer with layer of
stuff
• Implant
– Shoots ions into silicon with controlled energy
• Diffuse
– Heats wafer to diffuse implants
• Etch
– Uses plasmas or wet etches to remove silicon or oxide
• Polish
– CMP (Chemical Mechanical Polishing) uses wet slurry and rotating
wheels to smooth surface
Photolithography
•
•
•
•
A photoresist is spun onto the wafer
It is exposed using the mask with a stepper
The photoresist is chemically developed
Where the resist has been exposed, it is
washed away (this is a positive resist)
• The remaining resist blocks an implant or
etch
Fabrication step by step
• Wafer prep
• Active region isolation by LOCOS
or STI
• N and P Wells
• Threshold adjustment
• Gate and poly
• LDD
• Source & Drain diffusions
• Contacts
• Metal interconnect
• Higher metal levels & Passivation
Gettering
Gathers impurities
like Au, Na away
from surface by
diffusion. Scratched
back of wafer along
with oxygen
interstitials act as
nucleation sites.
Creates denuded
zone at surface.
Fabrication step by step
• Wafer prep
• Active region isolation by LOCOS
or STI
• N and P Wells
• Threshold adjustment
• Gate and poly
• LDD
• Source & Drain diffusions
• Contacts
• Metal interconnect
• Higher metal levels & Passivation
N-Select
Contact
N-well
Metal1
Poly
Via
Metal2
Active
(aka Diff)
Silicon nitride blocks Si oxidation
• Si3N4 can be deposited and patterned by
photolithography
• It can be very selectively etched without
etching silicon
• After patterning, it efficiently blocks
oxidation of silicon
LOCOS (Local Oxidation of Silicon)
Used extensively in
the past and still
used for many
processes
STI (Shallow Trench Isolation)
Harder than LOCOS but now used for deep submicron processes
PDG
PDG
FOX
Fabrication step by step
• Wafer prep
• Active region isolation by LOCOS
or STI
• N and P Wells
• Threshold adjustment
• Gate and poly
• LDD
• Source & Drain diffusions
• Contacts
• Metal interconnect
• Higher metal levels & Passivation
N-Select
Contact
N-well
P-well=!N-well
Metal1
Poly
Via
Metal2
Active
PDG
PDG
PDG
PDG
Fabrication step by step
• Wafer prep
• Active region isolation by LOCOS
or STI
• N and P Wells
• Threshold adjustment
• Gate and poly
• LDD
• Source & Drain diffusions
• Contacts
• Metal interconnect
• Higher metal levels & Passivation
N-select
PDG
!N-select (P-select)
PDG
Fabrication step by step
• Wafer prep
• Active region isolation by LOCOS
or STI
• N and P Wells
• Threshold adjustment
• Gate oxide and poly
• LDD
• Source & Drain diffusions
• Contacts
• Metal interconnect
• Higher metal levels & Passivation
PDG
N-Select
Contact
N-well
Metal1
Poly
Via
Metal2
Active
PDG
Gate oxide is tricky…
Nowadays is about 10 atomic layers thick
Dangling bonds create
havoc by allowing charge to
stick
Plummer, Deal, Griffen
Bravman
PDG
Poly
PDG
Fabrication step by step
• Wafer prep
• Active region isolation by LOCOS
or STI
• N and P Wells
• Threshold adjustment
• Gate and poly
• LDD
• Source & Drain diffusions
• Contacts
• Metal interconnect
• Higher metal levels & Passivation
LDD (Lightly Doped Drain)
• LDD is used in sub-micron processes to
reduce the electric field at transistor
drains
• It reduces damage caused by hot electrons
• It is necessary because power supply
voltage has not dropped as quickly as
process dimensions
PDG
PDG
Fabrication step by step
• Wafer prep
• Active region isolation by LOCOS
or STI
• N and P Wells
• Threshold adjustment
• Gate and poly
• LDD
• Source & Drain diffusions
• Contacts
• Metal interconnect
• Higher metal levels & Passivation
N-Select
P-Select=!N-Select Contact
N-well
Metal1
Poly
Via
Metal2
Active
N-select
PDG
!N-select
PDG
PDG
PDG
Fabrication step by step
• Wafer prep
• Active region isolation by LOCOS
or STI
• N and P Wells
• Threshold adjustment
• Gate and poly
• LDD
• Source & Drain diffusions
• Contacts
• Metal interconnect
• Higher metal levels & Passivation
PDG
N-Select
Contact
N-well
Metal1
Poly
Via
Metal2
Active
PDG
PDG
These ‘local interconnects’ are also called
Silicidation. They reduce resistance. Called Salicide
for Active and Polycide for Poly.
PDG
PDG
PDG
CMP
PDG
Fabrication step by step
• Wafer prep
• Active region isolation by LOCOS
or STI
• N and P Wells
• Threshold adjustment
• Gate and poly
• LDD
• Source & Drain diffusions
• Contacts
• Metal interconnect
• Higher metal levels & Passivation
PDG
N-Select
Contact
N-well
Metal1
Poly
Via
Metal2
Active
Contact
PDG
W=tungsten
Ti/N/W prevents ‘wormholes’ where Al makes spikes into Si
Metal1
Fabrication step by step
• Wafer prep
• Active region isolation by LOCOS
or STI
• N and P Wells
• Threshold adjustment
• Gate and poly
• LDD
• Source & Drain diffusions
• Contacts
• Metal interconnect
• Higher metal levels & Passivation
N-Select
Contact
N-well
Poly
Via
Metal2
Metal1
Active
Credits for illustrations
• Plummer, Deal, Griffin Silicon VLSI Technology
• A. Bergemont in Liu, Indiveri, Kramer, Delbruck,
Douglas, Analog VLSI
• van Zant, Microchip Fabrication