Transcript PowerPoint **

Asynchronous circuit design in
control driven approach
Name: Chi-Chuan Chuang
Date: 2013.05.01
Outline
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Control-driven
S and T element
Example – up counter
Example – while‐loops with choice
Example – sequencer with choice
Conclusion
Control-driven
• Requires more designer effort at the RTL level
• DFFs needs to be split into master/slave
latches
• The control logic has to be instantiated
manually as a network of S/T elements
Control‐driven Control and Registers
• A control‐driven system has registers with
selective read/writes and a control network
separate from the datapath
dr register (ki = 1)
01
1
01
0
10
1
0
01
0
dr register (ki = 0)
0
1
0
01
0
0
0
1
0
Comparison
Type
Area (transistors)
Data‐driven Half‐latch
34
Data‐driven FF
102 (!)
Control‐driven SR register
28
Diagram
Generally, control‐driven designs will have
lower transistor counts and lower energy than
data‐driven designs
S and T element
• Use to connect a chain of these elements to
form a sequencer with the la output of one
element connected to the lr input of the next
element
S element
0
0
1
0
0
T element
0
0
0
0
0
S and T element (cont.)
• Or (output) is typically used to trigger a read
on one or more registers
• Oa (input) is connected to the output of the
ack network for the destination registers
• T‐element offers more concurrency than
S‐element as it asserts la+ when Oa+ occurs
(starts next sequencer element) thus
beginning the next datapath action while the
current datapath action is returning to NULL
Example – up counter (RTL)
Module vreadport
• vrport
– used by control‐driven designs to conditionally
access of external inputs
– It does not provide dummy values when its select
line is false
Two state sequencer
• State S0
– gates the external inputs
– reads the slave register
– updates the master register with the new counter
value base on the slave register value and the exte
rnal inputs
• State S1
– writes the slave register
– places the counter value on the out terminals.
Two state sequencer (cont.)
• The two‐state sequencer
– loopen
– seqelem_kib
– seqdum_kib
Module loopen and seqdum_kib
• loopen is used to form a repeated sequence of
actions
• The seqdum_kib is simply wires
and one inverter
Module seqelem_kib
• seqelem_kib
• The letter b in kib is used to indicate that this
comes from a low‐true ack network such as ge
nerated by the data registers, and has to
be inverted inside of the seqelem_kib
component
Example – up counter (gate)
Example – while‐loops with choice
while‐loops with choice (RTL)
while‐loops with choice (cont.)
• State S0
– Reads external ports
• States that compute a flag and test the flag
• If the flag is true, execute states S1 and S2
• If the flag is false, execute state S3 and returns
to S0
while‐loops with choice (cont.)
• whileloop2step first computes the flag that is
used to control the loop execution and then
reads and check the flag
• Signals connected to the whileloop2 are
single‐rail signals, except for the flag signal
which is dual‐rail
• tseqelem components can be S/T elements as
desired
Module whileloop2step
Module whileloop2step (cont.)
• If the while body only has one state. This impli
es that the while‐body can be implemented wi
th a wired‐sequential element, a seqdum com
ponent and the last tseqelem element can be
replaced by a seqdum component, too
Example – sequencer with choice
sequencer with choice (cont.)
• element U1 implements state S0 (writes the
flag)
• element U2 implements state S1 (reads the
flag)
• Sror2 component is a single‐rail OR2
– since only one sequencer element is activated,
this gate combines the done signals of these two
components to a single done signal that is then
used as the ack for sequencer element U2
Conclusion
• Not all RTL signals will be expanded to
dual‐rail signals
• Control‐driven RTL has both single‐rail and
dual‐rail components (Sequencer elements
are single‐rail)
• Usage of single/dual rail signals will be
expanded
Reference
• Uncle (Unified NCL Environment) user manual
Thanks for your attention