Test structures of the SOI detector

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Transcript Test structures of the SOI detector

Fully Depleted Monolithic
Active Pixel Sensor in SOI
Technology
Presented by
Wojciech Kucewicza
on behalf of
A.Bulgheronib, M. Cacciab, K. Domanskic, P. Grabiecc, M. Grodnerc,
B. Jaroszewiczc, M. Jastrzaba, A. Kociubinskic, M. Kozioł, K. Kucharskic,
S.Kutaa, J. Marczewskic, H. Niemieca, M. Sapora, D. Tomaszewskic
a
AGH-Univ. of Science and Technology, Al. Mickiewicza 30, 30-059 Krakow, Poland
b Università dell’Insubria, via Valleggio 11, 22100 Como, Italy
c Institute of Electron Technology, Al. Lotnikow 32/46, 02-668 Warsaw, Poland
W.Kucewicz
2004 Nuclear Science Symposium, Rome, October 16-22, 2004
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Outline
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Principle of the SOI sensor
Preliminary test of the small area SOI
sensors on the high resistive
substrates
Design of the full size SOI sensor –
layout and readout scheme
The SOI project is partially supported
by the G1RD-CT-2001-000561
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2004 Nuclear Science Symposium, Rome, October 16-22, 2004
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Principle of SOI monolithic detector
The wafer bonding technics was choosen
for SOI technology
Low resistivity
Low resistivity
SIO2
SIO2
Termochemical
bonding
SIO2
SIO2
High resistivity
High resistivity
1-1,5 mm
Thin low resistivity layer – readout
electronics circuit
High resistivity support – sensitive area
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SIO2
SIO2
High resistivity
2004 Nuclear Science Symposium, Rome, October 16-22, 2004
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Principle of SOI monolithic detector
The idea:
Integration of the pixel detector and
readout electronics in the waferbonded SOI substrate
Electronics  Device layer
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Low resistive
(9-13 cm, CZ)
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1.5 mm thick
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Standard CMOS technology
Detector  Support layer
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High resistive
(> 4 kcm,FZ)
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300 mm thick
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Conventional p+-n
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DC-coupled
W.Kucewicz
2004 Nuclear Science Symposium, Rome, October 16-22, 2004
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Motivation
Advantages of the SOI detectors:
The SOI sensor may merge the advantages of the
monolithic and hybrid detectors
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As a monolithic device eliminates bump-bonding process and allows
reduction of total sensor thickness  reduction of multiple scattering
Allows using high resistive detector substrates and operation in fully
depleted region  good detection efficiency, enables detection of
particles with limited range in the silicon without backthinning process
Gives possibility to use both type of transistors in readout channels 
increased flexibility of the design, design optimisation for different
application
W.Kucewicz
2004 Nuclear Science Symposium, Rome, October 16-22, 2004
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Test structures of the SOI detector
W.Kucewicz
2004 Nuclear Science Symposium, Rome, October 16-22, 2004
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Test structures of the SOI detector
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Small readout matrices (8x8) with associated
detector diodes or input pads for external signal
sources were fabricated on the SOI wafers at the
IET, Warsaw
Two readout channel configurations – with NMOS
transistor switch (cell dimensions 140x122 mm2)
and with transmission gate (140x140 mm2)
N_ROW_SEL
VDD
VDET
COL
IN
RES
VSS
ROW_SEL
Contact to the detector placed in the V-shape
cavity.
Row selection signals led by two parallel lines with
opposite polarization, body of the structure
densely grounded  reduction of the cross-talk
between the electronics and detector
W.Kucewicz
2004 Nuclear Science Symposium, Rome, October 16-22, 2004
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Detector Readout
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Row_sel shift register and reset logic
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Operation in un-triggered mode (for imaging applications)
Analogue serial readout organisation
Readout sequence similar to rolling-shutter but double sampling performed for every pixel
External subtraction of samples for CDS
Well defined integration time and short dead time
Exercised and validated on the prototype chip designed in commercial AMS 0.8 technology
Readout
pixel
Readout
pixel
Readout
pixel
Readout
pixel
Readout
pixel
Readout
pixel
Readout
pixel
Readout
pixel
Readout
pixel
Readout
pixel
Readout
pixel
Readout
pixel
Readout
pixel
Readout
pixel
Readout
pixel
Analog
Output
Dummy
pixel
CLK
RST
READ
Control block
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Current reference
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Column_sel shift register
2004 Nuclear Science Symposium, Rome, October 16-22, 2004
8
14 cm
SUCIMA_IMAGER
EEPROM
A18
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VIRTEXII
II
VIRTEX
.
XC2V1000
XC2V1000
4FG456CES
4FG456CES
(324I/O)
I/O)
(324
BANK_7
BANK_6
D24
A18
USB & 28 GPIO pins
BANK_1
BANK_0
SENSOR’S REPEATER
BANK_3
BANK_5
D16
CTRL
2004 Nuclear Science Symposium, Rome, October 16-22, 2004
SRAM
A18
2x256Kx16B
40 MHz
2x256Kx16B
CLK
SRAM
It provides: the CDS or last frame readout
mode, masking noisy pixels, subtracting
pedestals, suppressing signals bellow threshold
and writing data to the file.
BANK_2
BANK_4
GUI – developed in LabVIEW environment,
allows setting: the matrix size to be readout,
readout frequency;
D32
SENSOR
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JTAG
SRAM
XV18V04
2x256Kx16B
The DAQ is equipped with 4 independent
analogue input channels with 12 bit ADCs, 1MB
fast static RAM, the FPGA Virtex II
XC2V1000 chip for advanced algorithms and
the high speed USB 2.0 port for a fast data
transfer to and from a PC computer.
SRAM
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2x256Kx16B
Dedicated DAQ system called
„SUCIMA imager” was developed
for the SUCIMA project by INF
in Cracow.
9.5 cm
SUCIMA Imager DAQ for the SOI
Detector
328 USER’s I/O PADS
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Stand Alone Detector Diodes and
Electronics with Input Pads
Readout Electronics
Detector Diodes
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Pixel leakage current:
 From 200 nA down to 10 nA per
cm2 depending on the process
Transfer characteristics were measured with
external voltage pulse signal
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 Measured DC output dynamic range up
to 1.0 V
Detector full depletion voltage:
 60 V down to 50 V for different
iterations
1.0E-09
with NMOS transistor switch
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with transmission gate
 Measured DC output dynamic range up
to 1.8 V non-linearity at the middle
range was reduced in the latest
Comparison of transfer characteristics of readout
designs
2.0E+03
[V]
2.0
1.0E-10
1.5E+03
Vout [mV]
Leakage current [A/mm2]
matrices on SOI wafers
Vout
1.5
1.0E+03
1.0E-11
e7
g8
1.0
5.0E+02
0.5
1.0E-12
0
10
20
30
Detector bias [V]
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40
50
60
one-transitor switch
switch in the form of
transmision gate
0.0E+00
20 0.4
40
60 0.8
80 100 1.2
120
00
MIP
0.0
2004 Nuclear Science Symposium, Rome, October 16-22, 2004
140 1.6
160Vin180
[V]
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Tests with the Laser Light
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Laser light not focused, shining from the
backplane (biased by a metal mash)
Wavelength = 850 nm
4 ms wide light pulses – simulate
particles passing through detector active
volume (each corresponding to 3.4 MIP)
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Integration time = 1 ms
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Detector polarization=60V
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10 000 events recorded and averaged
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Linearity of Sensor Response
Input signal scaled assuming the sensor
gain of 11mV/MIP
Good detector sensitivity for the ionising radiation and linear
response as a function of the generated charge was observed.
W.Kucewicz
2004 Nuclear Science Symposium, Rome, October 16-22, 2004
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Tests with the 90 Sr Beta Source
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Sensor sensitivity tested with
90Sr
beta source
Measurements conditions: complete depletion
(Vdet= 70 V), integration time: Tint = 720 ms,
source placed at the top of the sensor.
Detector output signal amplified (k2.5) before
digitalisations
Gaussian distribution
of the noise
Landau distribution of
the measured signals
On-line CDS processing, off-line pedestal
subtraction, common mode suppression and
cluster search
Recorded Event
Cluster Size
The most probably value of
signal per MIP: 27 ADC
Noise for the seed pixels:
1.5 to 2 ADC
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Tests with the Alpha Particles
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Alpha source placed at the distance of 1 cm from the detector backplane
Initial energy of particles = 5.5 MeV
Detector fully depleted (VD=70V), integration time 720 ms
On-line CDS processing, off-line pedestal subtraction, common mode suppression and cluster
search
W.Kucewicz
2004 Nuclear Science Symposium, Rome, October 16-22, 2004
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Tests with the Alpha Particles
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Typical measured cluster pulse height  200 ADC – corresponding to about half
of the alpha particles initial energy.
Pedestal width – about 1.5 ADC, S/N for cluster pulse height 130.
Broad spectrum due to energy straggling in air.
Cluster Size
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Noise Spectrum
Alpha Spectrum
2004 Nuclear Science Symposium, Rome, October 16-22, 2004
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Design of a full size detector layout
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a)
b)
12mm
10.24mm
<0-63>
ADC
ADC
ADC
ADC
24mm
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Row_sel
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Col_sel
c)
Detector
cavity
ADC
24mm
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Dimensions: 24x24 mm2
128 x 128 = 16 384 channels
4 sub-segments with independent parallel analogue outputs
Cell dimensions: 150x150mm2
Possibility to extend to ladders with dimensions up to 72x24 mm2 and small dead
areas
24mm
12mm
10.24mm
<0-63>
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72mm
W.Kucewicz
2004 Nuclear Science Symposium, Rome, October 16-22, 2004
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Full size detector
24
mm
ADC
ADC
ADC
24
mm
ADC
W.Kucewicz
2004 Nuclear Science Symposium, Rome, October 16-22, 2004
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„Baby Detector”
– backup solution of the SOI sensor
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Smaller number of the transistors, simpler functionality:
 48 x 48 readout channels, area 1.2 cm x 1.2 cm, no digital control blocks
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Reset and Column/Row selection signal must be generated externally (NRow and
NColumn signals are generated internally)
Configuration of the analogue block is the same as on the main detector.
Two versions – with dashed guardring (like on the main chip) and continuous
guardring – reliability and effectiveness of both solutions will be compared.
Dashed guardring
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Continuous guardring
2004 Nuclear Science Symposium, Rome, October 16-22, 2004
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New Test Structure
New Test Structure exploits the
experience gained with the old test
structure. It consists of:
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Several units of the old test
structure for the crosscheck of
the parameters between different
wafers
Several units with different
transistor layouts for matching,
noise and radiation hardness
studies
Test structure for direct IV and
CV characteristics measurements
of the detector diodes
Small matrix of the sensor with
modified readout configuration
W.Kucewicz
2004 Nuclear Science Symposium, Rome, October 16-22, 2004
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New Test Structure
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Matrix of 16x16 readout channels with
reduced capacitance at the input node –
higher signal per MIP
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Readout electronics configuration the same
like on the main sensor
Input (charge integrating) capacitance
reduced by disconnecting the polySi plate
covering pixel cavity from the input and
connection to the VSS (in case of the short
between input and polySi layer no negative
influence of the faulty pixel on the
neighbours performance).
Estimated pixel contact capacitance: Cpixcon 
27 fF, estimated total input capacitance: Ctot
 190 fF  signal per MIP: S  14  15 mV
This circuit was also placed separately
(outside Test Structure chip) at several
localization on the wafer – another backup
solution in case of the problems with the big
detectors.
W.Kucewicz
2004 Nuclear Science Symposium, Rome, October 16-22, 2004
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New Test Structure
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Matrix of 8x16 readout channels with the
conventional CSA configuration
VDD
VDD
VDD
PB2
PB1
OUT
IN
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8x8 channels with the standard contact and 8x8
with the reduced input capacitance
Charge integration mode – controlled by RES signal
Global reset and sampling&hold
Signal: 140 mV/MIP, lower noise.
Weak DC feedback loop – stabilize the operation
point of the input transistor – no protection diode
required
Partial leakage current compensation is possible by
adjustment of the PBF – may operate for leakage
current of the order of 10nA/cm2 up to 100
nA/cm2
Auto-polarization of the feedback transistor
Single cell dimensions: 329 mm x 357 mm
Much more sensitive for the device characteristics
changes than the 3T cell
W.Kucewicz
VX
2004 Nuclear Science Symposium, Rome, October 16-22, 2004
VX
VSS
RES
PBF
VSS
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Summary
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An alternative solution of a monolithic active pixel detector, which allows
efficient detection in high resistive substrate, has been proposed.
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First small area SOI pixel sensors have been fabricated.
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The tests results prove:
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sensitivity of the test matrices for the MIP signals (measurements with
90Sr),
wide dynamic range (measurements with laser spot and alpha particles),
detector suitability for the detection of particles with limited range in
silicon (measurements with alpha particles),
effectiveness of the charge integration mechanism implemented in the
readout circuit.
Following the positive results of the tests of the small area SOI sensors a
larger and fully functional SOI sensor (128x128 readout channels, active area
of 2 cm x 2 cm, optimised for medical imaging applications) have been designed
and produced.
W.Kucewicz
2004 Nuclear Science Symposium, Rome, October 16-22, 2004
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