Transcript Implementation Protocol

Implementing WLAN MAC
protocol on FPGA
Projects Seminar
Students:
Adi Hackmon & Yaniv Biton
Supervisors:
Dr. Shlomo Greenberg
Mr. Arnon Musayel
Project Number: 371-06-12
14/06/06
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product
or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005
802.11 MAC using FPGA - Outline
Project Goal & Motivation
Hardware Components
Communication Protocols
Project Description
Implementation Protocol
Unit Level Design
Project Status
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product
or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005
Project Goal & Motivation
Motivation
 Wireless LAN’s are on the verge of becoming a mainstream
connectivity solution for a broad range of business customers.
 Adding WLAN technology to current Communication Processor
Module (CPM) is a necessary step, for implementation of wireless
network applications.
Project Goal
 Examining the possibility of combining WLAN technology based on
IEEE 802.11 in Freescale’s communication processor, by using FPGA
technology design that shortens the process of hardware
implementation.
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product
or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005
802.11 MAC using FPGA - Outline
Project Goal & Motivation
Hardware Components
Communication Protocols
Project Description
Implementation Protocol
Unit Level Design
Project Status
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product
or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005
PQ2 Communication Processor architecture
 SoC – System on a Chip.
 A 64-bit G2 core with MMUs and cache.
 A communications processor module (CPM) supporting:
ATM through UTOPIA interface, IEEE 802.3, Fast Ethernet, HDLC
and other transparent operations
 System services and memory interface.
G2
PowerPC
Core
System
Interface
Unit (SIU)
Communication Processor
Module (CPM)
Serial
channels
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product
or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005
60x Bus
PCI/Local
Bus
Field Programmable Gate Array (FPGA)
 FPGA – is an integrated circuit (IC) used for implementing digital
hardware. The end user can configure the chip to realize hardware
designs.
LCD
screen
Configurable
clocks
VirtexII
Power
Supply
JTAG
I/O
Ports
Reset
8 User
Leds
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product
or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005
802.11 MAC using FPGA - Outline
Project Goal & Motivation
Hardware Components
Communication Protocols
Project Description
Implementation Protocol
Unit Level Design
Project Status
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product
or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005
IEEE 802.11
 IEEE 802.11 refers to a family of specifications developed for
wireless LAN technology.
 It specifies an over the air interface between a wireless client and a
base station, or between two wireless clients.
 The 802.11 defines a medium access control (MAC) sublayer, MAC
management protocols and services, and a number of physical
layers (PHY).
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product
or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005
802.11 MAC Frame Types

Management frames:
 Used to leave or join the network, and to move association from access
point to access point






Control Frames:
RTS – Request To Send
CTS – Clear To Send
ACK – Acknowledgment
PS-Poll frames – When a mobile station wakes from a Power-Saving
mode.
Data Frames:
 WLAN frame structure
Bytes
2
2
Frame NAV/
Ctrl
ID
6
6
6
2
6
Address 1
Address 2
Address 3
Seqctl
Address 4
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product
or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005
0-2312
Frame Body
4
FCS
ATM Protocol
 ATM is based on transferring data in cells or packets of a
fixed size- 53 Bytes.
 ATM creates a fixed channel, or route, between
two points whenever data transfer begins
Bit 0
Bit 7
Header 1
ATM is less adaptable to sudden surges in network
traffic.
Header 2
The ATM supports bit rates of up to 155 Mbps.
Header 4
Header 3
User Defined
Payload 1
…
Payload 48
ATM Cell structure
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product
or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005
802.11 MAC using FPGA - Outline
Project Goal & Motivation
Hardware Components
Communication Protocols
Project Description
Implementation Protocol
Unit Level Design
Project Status
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product
or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005
Project Description
 Design a controller (MAC) on the FPGA that will coordinate a WLAN
PHY provided by “Intersil” with Freescale's PQ2.
 Design a module on the FPGA that converts ATM cells to Wireless LAN
frames and vise versa.
Freescale
PowerQuicc
FPGA (MAC)
ATM Cells
WLAN PHY
WLAN
Frames
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product
or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005
802.11 MAC using FPGA - Outline
Project Goal & Motivation
Hardware Components
Communication Protocols
Project Description
Implementation Protocol
Unit Level Design
Project Status
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product
or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005
Implementation Protocol
Reception: The WLAN PHY sends WLAN frames to the FPGA which
cuts the frames to 48 bytes packets to build ATM cells by adding a
header to each of the packets. The FPGA sends ATM cells to PQ2
which concatenates the data to form a valid WLAN frame.
WLAN frame
48 byte
of data
48 byte of
data
53 byte ATM cell
5 byte ATM header
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product
or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005
Implementation Protocol
Transmission: The PQ2 sends ATM cells to the FPGA which
removes the header of the cells and concatenate all of the cells to
build a WLAN frame for the PHY unit.
5 byte ATM header
48 byte of
data
WLAN frame
Variable
Length
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product
or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005
802.11 MAC using FPGA - Outline
Project Goal & Motivation
Hardware Components
Communication Protocols
Project Description
Implementation Protocol
Unit Level Design
Project Status
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product
or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005
Unit Level Block Diagram
FPGA MAC TOP
Tx
FIFO
UTOPIA Signals
UTOPIA
Interface
PHY
Interface
PHY
Signals
Control Unit
25 MHz
11 MHz
Rx
FIFO
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product
or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005
Unit Level Block Diagram
 UTOPIA Interface for ATM – implements the ATM UTOPIA
communication protocol to enable transmission of ATM cells from the
PQ to the WLAN PHY and reception of ATM cells from the WLAN PHY
to the PQ.
 8-bit data path operating up to 25Mhz.
 Asynchronous FIFO – supports different InOut clocks
The Tx FIFO purpose is to hold the WLAN frames the PQ wishes to
send through the WLAN PHY .
The Rx FIFO purpose is to hold the ATM cells received from the
PHY Rx Interface for the PQ.
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product
or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005
Unit Level Block Diagram
Control Unit – manages the transceiving of ATM fixed cells and
variable length WLAN frames.
A Timer module controls the traffic timing.
PHY Interface – implements the communication protocol between
the FPGA and the WLAN PHY to enable transmission of wireless
LAN frames from the FPGA to the WLAN PHY and reception of
wireless LAN frames from WLAN PHY to FPGA.
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product
or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005
802.11 MAC using FPGA - Outline
Project Goal & Motivation
Hardware Components
Communication Protocols
Project Description
Implementation Protocol
Unit Level Design
Project Status
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product
or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005
Project status
 Assembling the Hardware:
 Connecting the boards and studying their features.
 Learning the interface and software required for implementation.
 FPGA Design Process:
Learning the communication protocols: ATM, WLAN 802.11
Designing the Blocks: Tx phase and Rx phase.
Writing Verilog code: for the FPGA
 Verification: testing the logic performance.
 PQ2 microcode:
Writing a test for receiving & transmitting WLAN frames through ATM cells
 Integration:
 The completion of the project will be a presentation of Freescale's CPM
communicating through the Wireless Medium.
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product
or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005
Questions??
Adi Hackmon & Yaniv Biton
Project Number: 371-06-12
14/06/06
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product
or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005