Transcript Radiation tolerant ASICs development status.

Radiation Tolerant
DC to DC Converters
ATLAS Upgrade Week
CERN
10/11/2010
B.Allongue, G.Blanchot, F.Faccio, C.Fuentes,
S.Michelis, S.Orlandi
CERN – PH-ESE
Outline

DCDC converters for sLHC.
 Radiation tolerant ASICs development status.
 Development of DCDC Plug-in-Boards.
 EMC properties.
 Conclusions.
AUW Nov. 2010
G. Blanchot, PH/ESE
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Outline

DCDC converters for sLHC.
 Radiation tolerant ASICs development status.
 Development of DCDC Plug-in-Boards.
 EMC properties.
 Conclusions.
AUW Nov. 2010
G. Blanchot, PH/ESE
3
DC/DC converters for sLHC

Increased need for power at sLHC




New powering schemes



AUW Nov. 2010
Increased number of channels = more power needed.
Cabling density cannot be increased further on.
Power losses cannot be increased further on.
DC/DC converters offer a conventional solution to increase the
delivery of power to the front-end.
Radiation, magnetic field, material budget are specific constrains to
impose custom designs.
Front-end systems are sensitive to couplings: need to pay particular
attention to EMI issues.
G. Blanchot, PH/ESE
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Case Study: Short Strip Tracker
SC and optoelectronics
Rod/stave
10-12V
Module
2 Converter stage2 on-chip
Stage 1: On Module Buck DC/DC converter
Stage 2: On Chip Switched Capacitor
Development of buck converter prototypes at CERN
Radiation tolerant DC/DC ASICs.
EMC and board optimization.
Production of sample converters for systems.
Detector
Scheme based on 2 conversion stages:
Hybrid
controller
10-12V
Intermediate
voltage
bus(ses)
Converter stage 1 block
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Outline

DCDC converters for sLHC.
 Radiation tolerant ASICs development status. F. Faccio
 Development of DCDC Plug-in-Boards.
 EMC properties.
 Conclusions.
AUW Nov. 2010
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Embedded functionalities of
different prototypes
AMIS2
IHP1
IHP2
Next✱
✓
✓
✓
✓
Dead times’
handling
Fixed
Adaptive
(QSW)
On-chip regulator(s)
No
No
✓
✓
Soft Start
Simple RC
Simple RC with
comparators
Full sequence
with comparators
State machine
Over-I protection
No
No
✓
✓
Over-T protection
No
No
No
✓
Under-V disable
No
No
No
✓
Full control loop
✱Full
Adaptive
Adaptive
(QSW and CCM, (QSW and CCM,
sharp transition) smooth transition)
design complete at schematic level (including start-up and protection features simulated with
a behavioral model for the converter)
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IHP1 and IHP2

IHP1

First prototype in the IHP 0.25μm
technology - no on-chip regulators
and bandgap voltage (Vbg)
generator

Excellent performance

IHP2

Includes all on-chip regulators and
Vbg generator, plus over-current
protection

It uses ‘new’ LDMOS transistors
(different than IHP1) - change forced
by transition from generation 2 to 3
at IHP

High efficiency, but 2 relevant
problems observed

Additionally, ‘new’ LDMOS have
radiation tolerance issues
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IHP1
IHP2
Problems observed on IHP2

Although working well at first, DCDC samples destructively failed with no
warning when switching conditions were modified (Iload, Vin) or randomly
during measurements




This has been eventually traced to the onset of latch-up triggered by the cyclic forwardbiasing of the drain-bulk diode of the NMOS power transistor (normal behavior in a
synchronous DCDC)
The problem was not observed in IHP1, indicating that the ‘new’ LDMOS inject
significantly more current in the substrate
Corrective actions are possible at the layout level, but need to be verified
Samples irradiated with protons are not functional already after an
integrated fluence of 1E15 p/cm2

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Measurement of individual transistors showed that the ‘new’ LDMOS are
much more damaged by protons than the generation 2 devices tested in
2008-2009 (in particular the PMOS and the Isolated NMOS)
G. Blanchot, PH/ESE
SEB and SEGR test results
(IHP Generation 3)
Single Event Burnout (SEB) and Single
Event Gate Rupture (SEGR)


are potentially destructive events threatening
high-voltage transistors in a radiation
environment
Dedicated study done on ‘new’ IHP
LDMOS using a heavy ion beam

A large number of SEB events has been
observed for N LDMOS
•


Sensitivity observed for Vds as low as 8V and for
Heavy Ion LET as low as 10 MeVcm2mg-1
Cross-section (cm2)

No event observed for PMOS during the full
test (up to 13V)
LET (MeVcm2mg-1)
SEGR

No sensitivity measured on N and PMOS
Limit cross-section, no SEB observed
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Conclusion on IHP2

With respect to the former prototype IHP1, the differences that led to
relevant consequences were:

The change of N and P LDMOS to the ‘new’ Generation3 transistors

The use of Isolated NLDMOS transistors

The integration of the on-chip regulators and duplication of the buffers driving the
switches (all other layouts that might contribute to the observed problems remained
unchanged)

As a result, the converter suffers destructive failures due to latchup and is not
tolerant to the required level of displacement damage

Moreover, NLDMOS transistors suffer SEB potentially leading to catastrophic
failure in the DCDC (we ignore whether this would be an issue for Generation 2
transistors)

Further design of a full DCDC converter in the 0.25μm technology has to wait
until an appropriate set of LDMOS transistors has been qualified and brought to a
sufficient level of maturity.
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AMIS2

Former prototype in the ‘backup’
0.35um technology (design done in
2008)

Simple design without on-chip
regulator, but proved to be working
well and reliably (extensively used in
system tests)

Lower efficiency than IHP1 and IHP2

Radiation tolerance to both TID and
displacement damage verified to high
levels - but no data was available for
SEB-SEGR
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SEB test of AMIS2


Heavy Ions beam irradiation test
performed
Measurements done on both:


Individual NLDMOS transistor with protection
resistor in series (and external comparator)
Full switching AMIS2 converter (increasing Vin from
6 to 12V, Vout=2.5V, f=1MHz, L=500nH, without
load or with 0.5A load in some conditions). 2
samples exposed.

No SEB observed in any of the tests with
LET of 21 or 31 MeVcm2mg-1, up to a
maximum Vds of 12V

The 0.35μm technology is fully radiation
qualified and adequate for the integration
of a DCDC converter
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ASICs Status Summary

Three prototype DCDC converter ASICs, with increasing complexity, have
been produced and tested



The chosen circuit solutions have been verified and improved leading to higher efficiencies
and getting closer to a final complete design (with all protection features)
The design methodology has been improved with the addition of a behavioral simulation
approach considerably shortening simulation time (and allowing study of system stability)
With the introduction of ‘new’ LDMOS transistors, and of increased
on-chip functionality (regulators), the most recent prototype in the
0.25μm technology has problems incompatible with a final reliable and
radiation-tolerant design

Further developments in this technology have to wait the qualification and maturity of a set of
LDMOS transistors

Meanwhile, the successful full radiation qualification of the AMIS2 DCDC
in the 0.35μm technology indicates a safe path for the rapid development
of a radiation-tolerant converter.

AMIS3 has been submitted (due 02/2011), AMIS4 is under development.
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Outline

DCDC converters for sLHC.
 Radiation tolerant ASICs development status.
 Development of DCDC Plug-in-Boards.
 EMC properties.
 Conclusions.
AUW Nov. 2010
G. Blanchot, PH/ESE
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Noise Optimized Plug-in-Boards

DCDC plug-in board to be used with systems, providing:





A compatible form.

Compact design.

Power interface: connector or bonds.

In some cases: control logic (ON/OFF + PowerGood).
Control of the noise sources for lower conducted and radiated couplings:

Understanding of how electromagnetic fields are emitted from power loops and switching nodes.

Layout that minimizes the conducted and radiated noise.
Shielding:

to cancel E field couplings with front-end systems.

to mitigate the radiated B field down to compatible levels .
Cooling:
A thermal interface must be provided for cooling.
Several DCDC-PIB have been designed and produced (or in production now):



AUW Nov. 2010
AMIS2_DCDC: 2 versions with AMIS2 radiation tolerant ASIC, implementing noise cancellation techniques.

10V down to 2.5V rated 2A for the 0.13um ABCN or any other low power module.
SM01C: using a commercial LT3605 chip similar to AMIS2, 60 boards available by end 2010.

10V down to 2.5V rated 5A for the 0.25um ABCN modules in use today, with connector.
STV10: same design as SM01C, for bonded connections on the ATLAS stavelet, ready for prod.
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Noise Optimized Plug-in-Boards
PROTO5
AMIS2
SM01B
Pgood
Vout
GND
Vin
Enable

Board size reduction down to 26mmx13.5mmx9mm.


SM01C is 28.4x13.5x9mm for ATLAS supermodule.
Increased switching frequency: 2 MHz on AMIS2, 3 MHz on SM01B.
Efficiency vs load Current
1

Custom coil (industrially made): 250nH that will stand straight onto the
AMIS2 ASIC.
Vin =
Vin =
Vin =
Vin =
Vin =
Vin =
Vin =
Vin =
Vin =
SM01B
0.95
0.9
0.85
Custom shields: PE boxes painted with Cu loaded varnish; plastic boxes
with Cu coating under study.
0.8
Efficiency

0.75
0.7

Efficiencies above 80% achieved. SM01B reaches 87% at 2A, and is
still at 80% for 4A load current at nominal input voltage.
0.65
0.6
0.55
0.5
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0
1
2
3
Load Current(A)
4
5
17
7.5
8.5
9
9.5
10
10.5
11
11.5
12
Outline

DCDC converters for sLHC.
 Radiation tolerant ASICs development status.
 Development of DCDC Plug-in-Boards.
 EMC properties.
 Conclusions.
AUW Nov. 2010
G. Blanchot, PH/ESE
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Radiated Magnetic Field
Switching freq. = 1 MHz
L = 350 nH
Load = 1A.



AMIS2 not shielded
120
5
120
115
dBA/m
110
SM01B
105
100
95
90
85
80
120
115
110
105
100
95
90
85
80
1
1
2
115
115
110
110
105
105
100
100
95
95
90
90
385
85
1
3
2
4
5
80
Y
1
1
1
2
4
5
115
SM01B
AMIS2
>120
110
115
<100
<100
Comment
Y
1
115
115
110
110
105
105
100
100
95
95
90
90
385
85
5
1
ShieldedSM01B
coilwithout shield
only
120
Non EMC
optimized layout
EMC optimized
1
layout
2
1
1
PROTO5 unshielded with toroid
120
120
115
110
105
100
95
90
85
80
120
115
110
105
100
95
90
85
80
1
115
110
105
100
95
1
115
110
105
105
100
100
95
95
90
90
385
85
385
4
5
Y
1
3
2
X
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1
80
X
5
1
2
X
SM01B shielded
120
120
115
110
105
100
95
90
85
80
1
120
115
110
105
100
95
90
85
80
115
110
105
100
95
1
90
2
3
385
4
3
2
4
80
Y
2
5
90
2
3
SM01B shielded
110
80
Y
2
PROTO5 unshielded with toroid
120
115
3
2
1
X
2
4
5
120
115
110
105
100
95
90
85
80
5
X
80
SM01B without shield
120
115
110
105
100
95
90
85
80
4
80
Y
X
3
2
90
3
2
X
3
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80
Y
X
Y
1
2
3
2
dBA/m
PROTO5
Shielded
dBA/m
Unshielded
95
120
2
3
[dBµA/m]
5
Y
dBA/m
The radiated magnetic field is measured
along X, Y and Z axes with a 1cm loop
probe over a grid. The vector magnitude is
computed.
120
115
110
105
100
95
90
85
80
100
385
4
80
PROTO5 with shielded PCB toroid
120
120
115
110
105
100
95
90
85
80
105
2
X
dBA/m
1
dBA/m
3
110
3
3
2
X
PROTO5 with shielded PCB toroid
115
1
dBA/m
5
120
115
110
105
100
95
90
85
80
2
dBA/m
4
Y
1
120
115
110
105
100
95
90
85
80
2
3
AMIS2 shielded
120
1
dBA/m
dBA/m
AMIS2
AMIS2 shielded
120
dBA/m
AMIS2 not shielded
dBA/m
PROTO5
5
Y
1
3
2
4
80
Y
X
5
1
2
X
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AMIS2DCDC Conducted Noise
DM Comparison
CM Comparison
50
50
ATLAS Limit
40
30
CM AMIS2 10V 2A
Class A (Average)
Class B (Average)
CM Proto5Bis 10V 2A
30
Class A Limit
20
Class A Limit
20
Class B Limit
dBA
dBA
ATLAS Limit
40
DM AMIS2 10V 2A
Class A (Average)
Class B (Average)
DM Proto5Bis 10V 2A
10
Class B Limit
10
0
0
-10
-10
-20
-20
-30
1
10
30
3MHz peak
-11.5 dBuA
-30
1
Frequency [MHz]
10
30
Frequency [MHz]
To further mitigate the radiated fields, electric and magnetic near field couplings that take please within the DCDC
board and its components were modeled. Based on this, noise cancelling routing and placement topologies were
implemented onto a new generation of converters using the AMIS2 ASIC. On this, a shield is added.

Compared to Proto5:

AMIS2_DCDC has more than 20dB less CM
noise, of about 300 nA at 3 MHz.

Switch Frequency is now 3 MHz: there are less
harmonic peaks in the sensitive band.

Now complies with Class B with more than 20dB
of margin.
AUW Nov. 2010

The DM noise has also been reduced.

Barely visible.

Two peaks at 3MHz and 6 MHz only, with less
than 300 nA amplitude.

Now complies with Class B with more than 25dB
of margin.
G. Blanchot, PH/ESE
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Optimized AMIS2 DCDC on
UniGe Module
KEK Hybrid Stream 0 using DCDC AMIS2
90
 =559.7042
80
 =33.2355
70

60
50
40
30
20
10
0
300
Conducted noise test
350
400
450
500
550
600
650
700
Input Noise [ENC] @1fC
KEK Hybrid Stream 0 using DCDC AMIS2 Close
750
AMIS2_DCDC, shield:

Reference:

Conducted:

Radiated Corner:

Radiated Top:
ENC
560
560
558
614
Sigma
32
33
34
38
800
70
 =558.2779
 =33.894
60
VCC and VDD are each powered from two
different DCDC converter, without
regulator on VCC.
50
40
30
20
10
0
300
350
Radiated noise at corner
400
450
500
550
600
Input Noise [ENC] @1fC
650
700
750
800
KEK Hybrid Stream 0 using DCDC AMIS2 On Top
90
The AMIS2-PIB, induces 10% more noise
with respect to the reference
configuration, when two converters are
place straight on top of the hybrids.
 =614.365
 =37.9097
80
70
The improvement is very significant, and is
in line with the noise reduction observed
on the reference test stand (CM and DM
noise).
60
50
40
30
20
10
Radiated noise on top of hybrid
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0
300
350
400
450
500
550
600
Input Noise [ENC] @1fC
650
700
750
800
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SM01B DCDC on UniGe Module
KEK Hybrid Stream 1 using Linear PS REF1
90
80
 =560.1623
 =34.0556
Reference noise

70
60
50
40
SM01B shielded:

Reference:

3cm on bonds:

Radiated Top:
ENC
560
563
573
Sigma
34
33
36
30
20
10
0
300
90
80
350
400
450
500
550
600
650
700
750
KEK Hybrid Stream 1 using
SM01 with
Shield 3cm over Hybrid
InputDCDC
Noise [ENC]
@1fC
800
VCC and VDD are each powered from the same
DCDC converter, with regulator on VCC for the
analog power of the ABCN chips.
 =562.8619
 =33.6686
3cm from bonds
The SM01B, induces less than 2% more noise with
respect to the reference configuration, when the
converter is placed straight on top of the hybrids.
70
60
50
40
30
SM01B radiates more than AMIS2DCDC but less
noise is observed:
20
10
0
300
350
400
450
500
550
600
650
700
750
Input Noise [ENC] @1fC
KEK Hybrid Stream 1 using DCDC SM01 with Shield just over Hybrid
80
800
 =572.9926
Radiated noise on top of hybrid
 =35.8624
70


60

50
40

30
20
2 AMISDCDC vs 1 SM01B.
Setups are slightly different: distance from
DCDC to hybrid probably larger for SM01B.
No analog regulator for the AMIS2DCDC
test.
It is in both cases an excellent performance
for an extreme placement of converters.
10
0
300
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350
400
450
500
550
600
Input Noise [ENC] @1fC
650
700
750
800
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Conclusions

A radiation tolerant technology is now qualified, resulting in AMIS2 ASICs available for
applications that require less than 2A @ 2.5V.

Further developments going on with IHP for secodn source technology.

AMIS2 was succesfully integrated in a low noise plug-in module compatible with a tracker frontend prototype.

Alternatively, plug in converters based on the commercial LT3605 chip have been designed for
application that require today 5A maximum @ 2.5V, with perfromances very close to AMIS2 but
not radiation tolerant.

60 boards SM01C in production now, 20 due mid november, 40 due mid december.

Suitable for Supermodule tests.

A design to be bonded onto stavelets is now ready for production.

More information in the Staves session.
AUW Nov. 2010
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