Transcript Presentazione di PowerPoint

Front-end electronics
for silicon trackers
Valerio Re
INFN
Università di Bergamo
Dipartimento di Ingegneria
Sezione di Pavia
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
1
Outline
Processing of signals from semiconductor detectors:
general concepts (amplification, shaping) and electronic
noise
Discussion of fundamental design parameters of frontend electronics for silicon trackers: signal-to-noise ratio,
speed, power dissipation, radiation hardness,…
Architecture of mixed-signal integrated circuits for the
readout of silicon pixel and strip detectors for tracking
and vertexing in high energy physics experiments
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
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From a single semiconductor sensor…
Ionization sensor converts the
energy deposited by a particle to an
electrical signal. In a fully-depleted
semiconductor sensor, electron-hole
pairs are swept to electrodes by an
electric field, inducing an electrical
current.
Particle track
Position-sensitive detector:
Information about the coordinates
of the interaction point in a
segmented region (presence of a hit,
amplitude measurement, timing)
(single-sided or double-sided strip
detector, pixel sensors)
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
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…… to a full silicon tracker
Multiple layers of
segmented detectors
(pixel, strips) provide
space points to reconstruct
particle trajectories
20 cm
30 cm
40 cm
BaBar Silicon Vertex Tracker at the
Stanford Linear Accelerator Center,
1999-2008: CP violation in B meson decay
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
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Readout electronics
• Silicon strip detectors need miniaturization of frontend electronics
• They were the driving force for the development of
integrated circuits for these applications
This is a mixed-signal chip, with
128-channel analog processing, A/D
conversion, data storage and serial
data transmission.
The AToM chip was fabricated in
Honeywell rad-hard 0.8 mm CMOS
(300k transistors) for the readout of
the BaBar SVT (1998).
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Current CMS Tracker system
• Two main sub-systems: Silicon Strip Tracker and Pixels
– pixels quickly removable for beam-pipe bake-out or replacement
Microstrip tracker
Pixels
~210 m2 of silicon, 9.3M
channels
73k APV25s, 38k optical
links, 440 FEDs
16k ROCs (CMOS 250 nm,
2k olinks, 40 FEDs
27 module types
8 module types
~34kW
~3.6kW (post-rad)
TOB
TIB
~1 m2 of silicon, 66M
channels
Geoff Hall,
TIPP09
TEC
TID
PD
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
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Hybrid pixel sensors
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A mature technology: hybrid pixel sensors
• A pixellated sensor chip is connected to a
matching readout chip by an array of solder bumps
• Sensors
– Particle sensitive volume is a high resistivity silicon bulk
(1-10 kWcm, 250 mm typical thickness, thinner for
higher radiation hardness and less material), can be
fully depleted for fast charge collection by drift
– Typical pixel dimensions at LHC: 50 mm  400 mm (will
decrease for HL_LHC)
– Radiation-hard to 50 Mrad (hundreds of Mrad for
HL_LHC)
• Front-end chips (Deep submicron CMOS)
– For any event (particle hit in the sensor) provide pixel
position, timing, pulse amplitude
– Only a small number of pixels are hit in any event
– Analog pre-amplification, discrimination, time stamping,
digitization, zero suppression (sparsification)…
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FE-I4 readout chip for pixel sensors
in ATLAS IBL
20.2 mm
Test pads
16.8 mm
(from Marlon Barbero,
“FE-I4 chip development
for upgraded ATLAS pixel
detector at LHC”, PIXEL
2010 workshop)
CMOS 130 nm mixedsignal chip
336×80
pixel array
Store hits locally in
region until L1T.
Periphery
2 mm
Digital readout of hit
pixels with analog
information (signal
amplitude) and time
stamp
IO pads
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
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FE-I4 readout chip for pixel sensors
in ATLAS IBL
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FE-I4 readout chip for pixel sensors
in ATLAS IBL: the analog pixel cell
FDAC
TDAC
4 Bit
Vfb
+
5 Bit
local
feedback
tune
Vfb2
feedbox
Inj0
Cf2
NotKill
+
HitOut
Cc
injectIn
Amp2
Preamp
Inj1
local
threshold
tune
+
feedbox
Cf1
Cinj1
Vth
-
Cinj2
Preamp
50 mm
Amp2
TDAC
discri
FDAC
Config Logic
150 mm
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FE-I4 pixel cell layout
250 mm
synthezised digital region (1/4th )
discri
Preamp
FDAC
50 mm
Amp2
TDAC
Config Logic
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Analog front-end design
for detector charge measurements
Radiation detectors
A measure of the information appears in the form of an electric
charge, induced on a set of two electrodes, for which ultimately
only one parameter (capacitance) is important.
Front-end electronics
amplifying device
(charge-sensitive preamplifier)
filtering, signal shaping
optimize the measurement of a desired quantity such as
signal amplitude as a measure of the energy loss of the
particle
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Effect of electronic noise on charge measurements
Inherent to the conduction of current in an amplifying device is a
random component, depending on the principle of operation of the
device.
This random component (noise) associated with amplification gives
an uncertainty in the measurement of the charge delivered by the
detector or of other parameters such as the position of particle
incidence on the detector.
Compromises must be made in very large and complex detector
systems such as modern silicon trackers.
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
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Statement of the problem of
front-end electronics
Measurement of a charge delivered by a capacitive
source with the best possible accuracy compatible
with noise intrinsically present in the amplifying
system, and with the constraints set by the different
applications.
(noise - power - speed)
The discussion of design of front-end electronics will
be based on the nuclear electronics noise theory.
(basic equations recalled for discussion purposes)
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Basic element of modern electronics:
the MOSFET
• Three-terminal device: an electrode controls the current flow
between two electrodes at the end of a conductive channel.
• The transconductance gm = dID/dVGS is the ratio of change in the
output (drain) current and of the change in the potential of the
control (gate) electrode
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MOSFET essential parameters:
the transconductance gm
100
Weak inversion law
m D
g /I [1/V]
Strong inversion law
Typical operating point
in low-power pixel
sensor readout
10
CMOS 90 nm
In weak inversion:
N-channel MOSFET (NMOS)
ID
gm 
nVT
w/l = 40/0.2
1
10
-6
10
-5
Under reasonable
power dissipation
constraints, devices in
deep submicron CMOS
operate in the weak
inversion region
10
-4
10
-3
(n =1.2 in 100-nm scale
CMOS)
I [A]
D
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MOSFET essential parameters:
channel thermal noise
Thermal noise arises from random velocity fluctuation of charge
carriers due to thermal excitation. The spectral density (noise power
per unit frequency bandwidth) is white, i.e. frequency independent. In a
resistor, this can be modelled in terms of a fluctuating voltage across
the resistor, or of a fluctuating current through the resistor.
R
de2R
 4kTR
df
R
di2R 4kT

df
R
The channel of a MOSFET can be treated as a variable conductance.
Thermal noise is generated by random fluctuations of charge carriers in
the channel and can be expressed in terms of the transconductance gm.
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
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MOSFET essential parameters:
channel thermal noise
Thermal noise in a MOSFET can be represented by a current generator
in parallel to the device, or by a voltage generator in series with the
gate (fluctuation of the drain current can be seen as due to
fluctuations of the gate voltage).
en
den2 4kT 

df
gm
in
din2
 4kT gm
df
k = Boltzmann’s constant, T = absolute temperature
 = coefficient ( 1) dependent on device operating region, short
channel effects…
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Acquiring the signal from the sensor:
the charge-sensitive preamplifier
• The detector signal is a current pulse i(t) of short duration
• The physical quantity of interest is the deposited energy, so one
has to integrate the sensor signal
i(t)
CD

ES  QS  i(t )dt
• The detector capacitance CD is dependent on geometry (e.g. strip
length or pixel size), biasing conditions (full or partial depletion),
aging (irradiation)
• Use an integrating preamplifier (charge-sensitive preamplifier), so
that charge sensitivity (“gain”) is independent of sensor
parameters
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
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Acquiring the signal from the sensor:
the charge-sensitive preamplifier
Circuit for charge
restoration on the
feedback
capacitor
CF
_
Q i(t)
CD
0
Q/Cf
This guarantees a return to baseline
of the preamplifier output, avoiding
saturation.
It can be achieved with a resistor RF
or, in an integrated circuit, with a
CMOS circuit (transconductor).
Compensation of detector leakage
current can also be performed in the
preamplifier feedback (dc coupling)
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
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Acquiring the signal from the sensor:
the charge-sensitive preamplifier
RF
gm
gm
1

t
Q t
C
Q
vu,pre (tv)u,pre (t)e RF CF e F
CF
CF
CF
Q i(t)
CD
Output voltage signal
_
Time
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Forward gain stage: CMOS version
• The forward gain stage is an inverting amplifier which can be
based on the common source configuration
_
D
G
gm vGS
VDD
R
vin
rDS
R
S
vout
vout
  gm rDS // R 
vin
rDS  (ID)-1
rDS  L (device gate length)
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
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Forward gain stage: CMOS version
• A higher forward gain can be achieved with a folded cascode
configuration. A smaller current in the cascode branch makes it
possible to achieve a high output impedance.
• An output source follower can be used to reduce capacitive loading
on the high impedance node and increase the frequency bandwidth
(high gain in a large frequency span)
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
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CMOS feedback network
• Single feedback MOSFET
Reset switch
Linear resistor
Reference voltage
Control signal
CF
CF
_
Q d
.
CD
Can be used when you can reset
the preamp at fixed times
_
Q .d
R ON 
CD
L
1
W m N COX VGS  VT 
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CMOS feedback network
• A large feedback resistor is needed for low noise, since
2
diR
df

4kT
R
• It is difficult to fabricate a large physical resistor in monolithic
form, or to effectively control the resistance of a MOSFET
biased in the linear region
• A large resistor can be simulated by a CMOS circuit, such as a
transconductor, which can be considered to be equivalent to a
+ VDD
resistor R = 1/Gm
iF
gm
iF = (gm/2)vOUT = Gm vOUT
I/2
CF
_
Q i(t)
CD
VOUT
VREF
M2
M1
VOUT
I
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Compensation of detector leakage current
• Irradiated, dc-coupled pixel sensors may have a considerable
leakage current, which may saturate the feedback transconductor
or, flowing in the feedback resistor, considerably affect the dc
voltage at the preamplifier output.
• A CMOS circuit can be designed to accomodate for this leakage
current. A popular solution is the following:
The feedback capacitor is
discharged linearly by a constant
current. The output signal lends
itself to an amplitude-to-time
conversion (time-over threshold
measurement).
vout
-Ib/CF
Vth
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
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Processing the signal from the sensor:
the shaper/filter
• Signal shaping: the voltage step at the preamplifier output has to
be constrained to a finite duration to avoid pileup of successive
signals
Shaper output
Output voltage signal
Shaper Output Voltage
Preamplifier output
Time
Time
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
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Processing the signal from the sensor:
the shaper/filter
• A unipolar “semigaussian” shaper can be built with 1
differentiator (high pass) and n integrators (low-pass).
Feedback resistor
• This is a compact (n=1) implementation:
From the
preamplifier
0
Differentiating
capacitance
implemented with a
CMOS device or circuit
R2
C2
Q/Cf
_
C1
Bandwidth-limited
gain stage
t

Q t 
vu (t)  A
e
CF 
For correct values of
the time constants
associated to the
s
feedback
T (s)  network and
1 stage,
 s 2 the
to the gain
transfer function has
two coincident poles
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
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Processing the signal from the sensor:
the shaper/filter
Frequency domain
Time domain
Increasing n
Time
Gain
Shaper Output Voltage
• In the AToM (BaBar) and FSSR2 (BTeV) chips (microstrip
trackers), a second order (n=2) shaper was implemented with an
additional integrator before the shaper.
• For an nth-order unipolar shaper (higher n: more symmetrical
pulse, higher signal rates for the same peaking time):
s
n t
T ( s) 
Q t

vu (t)  A
  e

1  s n
CF   
Increasing n
Frequency
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
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“Shaperless” analog channel
• In future applications for imaging and vertexing detectors, very
small pixels may be needed (< 10x10 mm2) with no room in the pixel
for a shaper
• Under these constraints, a viable solution consists in artificially
reducing the preamplifier bandwidth
Preamplifier response to an 800 e- pulse
Preamplifier
22T
14T
-G(s)
CF
Vt
Discriminator
Preamplifier output [V]
0.12
0.1
i =3 nA
F
0.08
iF=5 nA
i =10 nA
0.06
F
i =15 nA
F
0.04
0.02
0
-0.02
0
iF
5
10
15
20
25
30
t [ms]
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
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Charge measuring system and the
effect of noise Filter minimizes the
CF
eN
Q .d
CD
iN
Charge collection is
very fast in
semiconductor
detectors
Filter T(s)
Shaper
measurement error with
respect to noise and the
effect of pulse overlap
(finite duration)
Ci
Ionization detectors
can be modeled as
capacitive signal
sources
Vmax  Q
tP
Noise arises from two uncorrelated sources at the
input (series and parallel noise):
SeN   AW 
Af
f
SI   BW
N
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
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White series noise

AW  4kT
gm
1/f series noise
A1/ f 
Af
f
Noise sources
White noise in the main current
(drain, collector) of the input
device
other components in the input
stage
stray resistances in series with
the input
1/f component in
the drain current
Series noise sources
White parallel noise
BW  2qIdet  2qIG(B) 
4kT
R
Shot noise in detector leakage
current
shot noise in input device gate
(base) current
thermal noise in feedback resistor
Parallel noise sources
Current generators at the
preamplifier input
Voltage generators at the
preamplifier input
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
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Shot noise
Shot noise is associated to device currents when
charge carriers have to cross a potential barrier (P-N
junctions in diodes and bipolar transistor)
SI   2qI
In irradiated silicon detectors, leakage current and
the associated shot noise may strongly increase
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1/f noise
gate
oxide
drain
source
substrate
Interaction between charge carriers in the MOSFET
channel and traps close to the Si-SiO2 interface leads to
fluctuations in the drain current.
This can be modeled with a noise voltage generator in
series with the device gate, with a 1/f spectral density.
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
35
Effect of electronic noise on charge
measurements
V
Q
Ideally indefinitely narrow
distribution of detector charge
(neglecting statistics in energy deposition
and charge creation)
Vu
Broadening of pulse amplitude distribution
at the shaper output due to electronic noise
Because of electronic noise, the signal amplitude at the shaper
output has a Gaussian probability density function
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
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Effect of electronic noise on
charge measurements
referred to the input
(dividing by the analog channel
charge sensitivity)
V
Q
Vu
Q
The signal amplitude at the output
V
Q
Q
of the linear analog channel is
S/ N  u 

 Q
V Q ENC
characterized by a Gaussian probability
density function
Equivalent Noise Charge = standard deviation in the
charge measurement
charge injected at the input producing at the output of
the linear processor a signal whose amplitude equals
the root mean square output noise
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
37
Equivalent Noise Charge (ENC)
CF
eN
Q .d
CD
iN
Filter T(s)
Shaper
Ci
Vmax  Q
tP
The mean square value of the noise voltage at the shaper
output can be calculated as follows:
vu2,N



0
Su (  )df 

0





T
j


S
(

)

T
j


S
(

)
eN
IN
IN
 eN
df
2
2
Af

C D  Ci  CF 2
( AW 
 T  j  
2

0 
2
CF
f
)  T  j 
2

 BW df 
2 2
 CF

1
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
38
Equivalent Noise Charge (ENC)
 AW
 Af
CD  Ci  CF 2
C F2
CD  Ci  CF 
2
C F2
1 
2
T  j  d 
2 0


0
T  j 

1 
A
2
T  j  d  1
2 0
tP


0
T  j 
2



1
2 0
d  A2
T  j 

2
2
d  BW


1
C F2 2 0
1
T  j 

2
2
d
tP = peaking time of the
signal at the shaper output
A1, A2, A3 = filter-dependent
coefficients
2
d  A3t P
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39
Equivalent Noise Charge (ENC)
ENC 
vu2,N
Ch arg e
sensitivit y
A1
2
2
2
2
ENC  vu,N  CF  AW CD  Ci  CF
 Af CD  Ci  CF 2 A2  BWA3tP
tP




CT = C D + C i + CF
= total capacitance at the preamplifier input
In a well designed preamplifier, the noise is determined
by the input device.
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
40
Equivalent Noise Charge (ENC)
ENC 
2
AW CT2
A1
 A f CT2 A2  BW A3t P
tP
White series noise:
Neglecting noise in parasitic resistors:

AW  4kT
gm
 = 0.5 (BJT)
 = 2/3 (Long channel FETs)
  1 (Short-channel FETs)
White parallel noise:
BW  2qI
I = IB
(BJT)
I = IG
(gate tunneling current
in nanoscale CMOS)
I = Ileak Detector leakage current
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
41
Equivalent Noise Charge (ENC)
ENC 
2
2
AW CT
A1
2
 A f CT A2  BW A3t P
tP
Series 1/f noise (MOSFET):
Af 
Oxide capacitance
per unit gate area
Kf
COXWL
1/f noise parameter;
depends on the gate oxide
quality
Transistor geometry
(gate Width and Length)
The ENC contribution from 1/f noise is independent of the
peaking time of the signal at the shaper output; it is weakly
dependent on the shape of the transfer function of the shaper.
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
42
• In trackers for high luminosity colliders, event rate is very high,
and the peaking time has to be short (< 100 ns).
• White series noise is usually dominant here, except with
irradiated sensors, where leakage current (and the associated
shot noise) may increase to a very large extent.
ENC [e rms]
1000
total ENC
100
1/f series noise
white series noise
10
0.01
0.1
parallel noise
1
10
100
1000
t [ms]
P
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
43
ENC: BJT vs MOSFET
• Bipolar transistors have a larger gm/I ratio with respect to MOSFET,
which means a lower series white noise for a same current
• BiCMOS (SiGe) technologies are an appealing alternative for fast
readout systems; since they are less dense (and more expensive) than
CMOS, their use is mostly limited to strip front-end chips
10
4
ENC [e rms]
MOS
BJT
1000
I = 200 mA
C = 15 pF
T
100
1
10
100
1000
t [ns]
P
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
44
Gate leakage current shot-noise in
nanoscale CMOS
SIG(f) 2qIG
90 nm CMOS process:
• Current density = 1 A/cm2
• W = 1000 mm
• L = 0.1 mm
 IG= 1mA
 SIG=2qIG=0.56 pA/Hz
Non negligible noise contribution
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
45
Rad-hard, low-noise charge preamplifier design:
short strip readout with 90 nm electronics, NMOS input


2
CMOS looks not too
ENC   AW

different from bipolar

transistors

Kf
A1
 2

A2 CT  2qIG  A3  tP
tP C WL

OX

White noise
ID
Weak inversion region: g m 
nVT
1/f noise
Parallel noise
(n =1.2 in 100-nm scale CMOS,
n=1 in bipolar transistors)
 Expect ~ 20% higher ENC
contribution from white series
noise for the same device current
VT
2kT
2
AW  n
 n 2kT
gm
ID
Series white noise is dominant at
tP < 100 ns
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
46
Noise and detector capacitance
White and 1/f series noise terms
(dominant in CMOS) give a
contribution to ENC linearly
increasing with the detector
capacitance (CT =CD + CIN + CF).


ENC 2   AW



A1
 2

A2 CT
tP C WL

OX

Kf
2000
3000
FSSR2 chip,
input device: NMOS, W/L = 1500/0.45
2000
1500
CD = 57 pF
CD = 43 pF
1000
CD = 32 pF
1500
ENC [e rms]
ENC [e rms]
2500
t = 85 ns
P
t = 60 ns
P
1000
t = 125 ns
P
500
CD = 20 pF
500
NMOS, W/L = 1500/0.45
CD = 10 pF
CD = 0
0
0
60
80
100
120
Peaking time [ns]
140
0
10
20
30
40
C [pF]
D
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
47
Capacitive matching
It is possible to minimize ENC by a correct choice of the
dimensions of the preamplifier input device (gate width
W and length L)
Conditions for optimum matching between the preamplifier
input capacitance (CIN = COXWL) and the detector
capacitance CD depend on the input device operating region
(most often, weak or moderate inversion) and on which
series noise contribution is dominant (white or 1/f)
This optimization has to comply with constraints on the
power dissipation, which limit the drain current in the
input device (in weak inversion, AW  1/gm  1/ID)
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
48
Capacitive matching in a deep
submicron technology
1
(C /C D)
IN
opt
0.8
0.6
1/f noise dominant
L = 0.35 µm
CD = 10 pF
ID = 250 µA
0.4
PMOS
0.2
At tP = 10 - 100 ns
CIN ≈ 0.1 CD gives
minimum ENC
NMOS
0
White noise 10
dominant
100
1000
104
105
tp [ns]
0.18 µm technology
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
49
Capacitive matching in a deep
submicron technology
Optimum ENC and input NMOS gate width in the CD
region of pixel detectors
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
50
Extracting a hit information from the
sensor signal: the discriminator
• Binary readout: hit/no hit information from a discriminator
• This can also be associated to an ADC system, providing an
information about the charge delivered by the detector
PREAMPLIFIER
CF
SHAPER
Q.d
CD
DISCRIMINATOR
Vth
Vth
• In a multichannel readout chip, channel-to-channel threshold
variations due to device mismatch may degrade detection
efficiency and spurious hit rate
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
51
Efficiency and noise occupancy
• An excessive threshold dispersion can lead to channels with high
noise hit rate or reduced efficiency in signal detection.
Noise
gaussian
distribution
Discriminator threshold
Count rate
( = ENC)
Landau
distribution
of detector
charge for
a M.I.P.
Most probable value
depends on:
detector thickness
(80 e-h pairs/mm
for 300 mm
thickness)
charge collection
efficiency
(degraded in
irradiated silicon)
Detector charge
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
52
Threshold dispersion
• Discriminator threshold dispersion is given by statistical
variations of the threshold voltage of MOSFETs in the
differential pairs used in the discriminator input stage:
2 Vth  
A2
vth
WL
+ VDD
Large area transistors
help reduce the effect
of threshold mismatch
M4
vOUT
M3
vth
vin
M2
M1
I
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
53
• As for the noise, the discriminator threshold and its dispersion
(divided by the analog channel charge sensitivity) can be treated
in term of input-referred charges, Qth and qth respectively.
• For a second-order semigaussian shaper, and series white noise as
the dominant contribution to ENC, the frequency of noise hits can
2
be calculated as:
Qth
3  2ENC2
fn 
e
tP
• In practical conditions, the number of noise hits can be kept at
acceptably low values by satisfying this condition:

sig
 4 ENC  qth
th
Q

• To maintain an adequate efficiency, a channel-by-channel
threshold adjustment may be necessary (threshold DAC in the
pixel cell)
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
54
Analog-to-digital conversion
S
R
PREAMPLIFIER Vth
CF
SHAPER
COMPARATOR
Latched
binary
output
ToT
counter
Q.d
CD
Time-OverThreshold
binary code
clock
Vth
A
Cst
D
Amplitude
information
(binary code)
Flash, ramp, SAR,……
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
55
Time-Over-Threshold (ToT) analog-to-digital conversion
The ADC conversion of ToT is straightforward, avoiding circuit complexity
in a chip with a very high functional density.
Compression type characteristic
Pseudo-linear characteristic
3
Comparator Out
0.5
2.5
out
Vout [V]
0
-0.5
Shaper Out
1.5
-1
1
-1.5
-1
0
1
2
3
4
Time
10
0
500
1000
1500
2000
t [ns]
1200
1000
TOT [ns]
8
ToT /tp
2
6
4
800
600
400
200
2
0
0
0
10
20
30
40
Qin/Qth
50
60
70
0
500
1000
1500
Vout [mV]
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
56
Readout architecture
Digital information of hit signals is further processed by circuitry
associated to each pixel (strip) and at the chip periphery. Position
(pixel or strip address), timing (time stamp) and possibly pulse
amplitude (from ADC) information must be provided.
All architectures perform data sparsification, processing only data
from channels where the signal exceeds the discriminator threshold
Often, a trigger system selects only a fraction of the events for
readout, reducing the data volume sent to the DAQ. In this case,
information for all hits must be buffered for some time, waiting for a
trigger signal (delay of a few ms).
Triggerless (data push architectures) are also available. All hits are
read out immediately (as long as the rate is not too high). This allows
the tracker information to be used for Level 1 Trigger
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
57
00 11 110
00
SRAM
BUFFER
CF
Q .d
CD
TOT CASCADED
COUNTER BUFFERS
SHAPER
PREAMPLIFIER
0
00
0 00 11 11 0
00
0 11110 0
Block diagram of the front-end chip AToM
for signal processing in the BaBar Silicon Vertex Tracker
COMPARATOR
HIT
INFORMATION
BUILDING-UP
DATA
TRANSMITTED
SPARSIFICATION
Vth
DATA
FORMATTING
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58
AToM digital section
6
5
4
3
2
1
0
-1
Channel
address
-1
0
1
2
3
Time [µs]
1 start bit
4 chip address
1 read event/register
5 trigger tag
5 trigger time
4
5
Analog
section
Trigger L1
15 MHz
60 MHz
Time Stamp
Counter
Serial output
Output
buffer
TOT
Counter
193 RAM cells
7 channel number
5 time stamp
4 ToT
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59
FSSR2 chip
(triggerless strip detector readout)
Front-End
Core Logic
Programming
Interface
Data output
Interface
7.5 mm x 5 mm, input pads with 50 mm pitch
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60
FSSR2 block diagram
To silicon s trip de te ctors
1
16 se ts of logic e a ch
ha ndling 8 a na log cha nne ls
BCO ctr
Core Logic
Clock
P
rogra
mma
ble
DACs
Control
Re giste rs
Logic
P rogra mming Inte rfa ce
BCO clock
16
I/O
Ne xt
Block
Word
Word Se ria lize r
Ste e ring Logic
Re a dout High S pe e d
clock
Output
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
Core
128 cha nne ls of a na log circuits
Data Output Interface
• FSSR2 Core
– 128 analog channels
– 16 sets of logic, each
handling 8 channels
– Core logic with BCO
counter (time stamp)
• Programming Interface
(slow control)
– Programmable registers
– DACs
• Data Output Interface
– Communicates with core
logic
– Formats data output
61
The devil is in the details: integration of
mixed-signal functions in a multichannel chip
• Non-ideal effects may degrade the performance of
low-noise analog circuits in strip or pixel readout
integrated circuit:
Interferences from digital signals (clocks,
commands, readout lines)
Voltage drops on interconnections distributing
power supply voltages across large area chips
………
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
62
Digital-to-analog interferences
• There are many ways by which interferences can propagate through the
chip substrate…
• These effects can be mitigated by using differential, low-level digital
signals (LVDS), by isolation techniques, by layout tricks (separated
analog and digital power and signal routing) …
I. A. Young
(Intel), “Analog
mixed –signal
circuits in
advanced
nanoscale
CMOS
technologies for
microprocessors
and SoC”, 2010
ESSCIRC
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
63
An example of system issues in front-end chip
design: voltage drop on power supply lines
Analog VDD
Reference currents provided
by DACs in the chip periphery
are mirrored inside pixel cells
by means of current mirrors. A
voltage drop of a few mV
along the ground line causes
that the first and last pixels in
column get different reference
currents.
This has a detrimental effect
especially for the cells far
away from the chip periphery.
Analog ground
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
A solution to the problem of voltage drop on power
supply lines
This problem can be solved by
transferring a reference voltage
in each pixel, so that a MOSFET
in a pixel cell current source is
biased at the same gate-tosource voltage as a transistor
in the periphery reference
network
M. Manghisoni et al., “High Accuracy Injection Circuit for Pixel-Level Calibration of
Readout Electronics”, 2010 IEEE NSS Conference Record
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
65
Microelectronics for semiconductor detectors:
nanoscale CMOS and 3D integration
New applications of semiconductor detectors in high energy physics (silicon
vertex trackers) and photon science (high-resolution imagers) set demanding
and often conflicting requirements on the front-end electronics
More electronic intelligence squeezed in smaller pixel cells, larger amount of
data stored in the chips and then transmitted outside, circuits operating at
lower power and standing higher radiation levels, minimum amount of material
and dead areas, ….
The potential of current microelectronic processes (including
interconnections) has to be exploited; this may even require to use different
technologies for different functions by 3D integration
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
66
Industry Scaling Roadmap for CMOS
• New generation every ~2 years with a = √2
• Lg (1970) 8 mm
(2007) 18 nm
HEP
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
67
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
68
Nanoscale MOSFETs
Lewyn et al,
“Analog
circuit
design in
nanoscale
CMOS
technologies”
, Proc. IEEE,
Vol. 97, no.
10, Oct.
2009.
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
69
CMOS scaling: why
Industrial microelectronic technologies are today well beyond the 100 nm
frontier, bringing CMOS into the nanoscale world
Digital performances (speed, density, power dissipation) are driving the
evolution of CMOS technologies towards a continuous shrinking of
physical feature sizes.
Analog performance remains essential for the processing of signals
delivered by semiconductor detectors.
Front-end electronics may benefit from scaling in terms of functional
density (small pitch pixels) and digital performance. Analog design is a
challenge (reduced supply voltage and dynamic range, statistical doping
effects, ………)
For a full integration of analog and digital circuits in the most modern
semiconductor technologies, design advances are needed to exploit the full
potential: digital signal processing may be used to overcome analog
limitations, analog circuits may be used to monitor the performance of
digital circuits and their power consumption.
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
70
CMOS scaling: how
Shrinking of gate length leads to
an increase in speed and circuit
density. To avoid short-channel
effects, drain and source
depletion regions are made
correspondingly smaller by
increasing substrate doping
concentration and decreasing
reverse bias (reduction of the
supply voltage)
Increasing substrate doping increases
the device threshold voltage: this is
overcome by decreasing the gate oxide
thickness.
Classical scaling ended because of gate
oxide thickness limits: in very thin oxides,
direct tunneling of carriers leads to a
large gate
leakage
current.
Valerio
Re - V Scuola
Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
71
Howa hs Moore’s law
e be n possibl
M. Bohr
(Intel),
“The new
era of
scaling in a
SoC world”,
ISSCC
2009.
Mechanical stress (compressive or tensile strain) is introduced in
the silicon channel to enhance carrier mobility and drive current.
Gate dielectric is made thicker (still reducing gate capacitance) by
using materials with higher dielectric constant than SiO2.
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
72
Gate leakage current in nanoscale
CMOS flavours and generations
These types of stresses increase
anddensity
hole populations
in the
Theelectron
gate current
is used to evaluate
impact
of the
gate oxide
thickness
reduction
energy
bands
where
they have
low on
thetunneling
static power
consumptionthrough SiO
probability
2
JG is
the
I
/WL
measured
at
V
=0
G
DS their
(in addition
to enhancing
IG ismobility
due to discrete
randomly crossing a
in the charge
channel)
potential barrier
Gate Current Density [A/cm2]
Interestingly, the gate leakage current is observed to decrease for the types of
stresses adopted by the industry in advanced CMOS (tensile and compressive
Gate
leakage
current
stress
for NMOS
and PMOS, respectively)
10
2
10
1
10
10
1 A/cm
2
NMOS
PMOS
NMOS
|V GS|=1.0
PMOS
V
0
-1
We made tests on 130 nm and 90
10-2
nm GP (General Purpose) transistors
-3
10
and on 65 nm LP (Low Power)
transistors (VDD = 1.2 V). These LP
-4
10
devices were optimized for a
reduced leakage (larger equivalent
10-5
oxide thickness, different level of
nitridation with respect to other
flavours, different
stress).
Oxynitride
gate allowssilicon
to reduce
tunneling effects
VDS=V BS=
0
Foundry B
GP devices
Foundry A
LP devices
130
90
Technology Node [nm]
Valerio Rechanges
- V Scuola between
Nazionale “Rivelatori
ed Elettronica”,
INFNtwo
– LNL,
15 – 19 aprilefoundries
2013
The gate current
90nm processes
from
different
65
73
A
A
B
B
CMOS 65 nm: the Low Power flavour
After the 250 nm (LHC) and the 130 nm node (LHC upgrades, XFEL,…), our
community appears to be very interested in the 65 nm CMOS generation:
several prototypes have been already fabricated and tested.
Among the wide choice of options of this technology, the Low Power flavour
is less aggressive than other variants (thicker gate oxide, smaller gate
leakage, higher voltage), and is more attractive for mixed-signal chips where
analog performance is an essential feature.
Critical aspects for analog design in nanoscale CMOS (with focus on LP
65 nm) for detector readout integrated circuits:
1/f noise
Interaction of charge carriers with
the gate oxide; tools for evaluating
the quality of the gate dielectric
Thermal noise
Charge carriers in the device channel
(short channel effects, strained silicon)
Radiation hardness
Radiation-induced positive charge in the
gate oxide and in lateral isolation oxides
Gate leakage current
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
Gate current in 130 nm and LP 65 nm
10-4
10-6
G
I [A]
10-8
1 A/cm
2
10-10
130 nm process
65 nm process
-12
10
NMOS W/L = 200/0.70, V = 0 V
DS
-14
10
0
0.2
0.4
0.6
V
GS
[V]
0.8
1
1.2
Noise in NMOS:
CMOS generations from 250 nm to 65 nm
1/2
Noise Voltage Spectrum [nV/Hz ]
100
1/f noise has approximately the same magnitude (for a same WLCOX)
across different CMOS generations. White noise has also very similar
properties (weak/moderate inversion).
1/f noise
K
2 (f) 
f
W/L = 2000/0.45, 250 nm process
S1/f
W/L = 1000/0.5, 130 nm process
COX WLf a f
W/L = 600/0.5, 90 nm process
W/L = 600/0.35, 65 nm process
10
• kf 1/f noise parameter
• αf 1/f noise slope-related
coefficient
C = 6 pF
IN
I = 100 mA
Channel thermal noise
D
NMOS
1
10
3
10
4
10
5
10
Frequency [Hz]
6
10
7
10
8
4k T
S2W  B ,
gm
• kB Boltzmann’s constant
  a W n
• γ channel thermal noise
coefficient
• T absolute temperature
• αw excess noise coefficient
In weak g  ID
m
inversion:
nVT
76
65 nm LP process: 1/f noise
In older CMOS times, PMOS transistors had a considerably lower 1/f noise
with respect to NMOSFETs. This difference tends to decrease with newer
CMOS generations.
In the 65 nm LP process, NMOS and PMOS have similar 1/f noise.
100
100
1/2
Noise Voltage Spectrum [nV/Hz ]
1/2
Noise Voltage Spectrum [nV/Hz ]
This could be explained by a “surface channel” behavior for both devices, and/or by
the fact that the gate dielectric nitridation decreases the barrier energy
experienced by holes across the silicon-dielectric interface. This would make it easier
for the PMOS channel to exchange charges with oxide traps.
NMOS
PMOS
10
65 nm transistors W/L=600/0.35
@ ID=50 mA, VDS=0.6 V
1
3
10
10
4
10
5
6
10
Frequency [Hz]
7
10
10
8
NMOS
PMOS
10
65 nm transistors W/L=600/0.10
@ ID=50 mA, VDS=0.6 V
1
3
10
10
4
10
5
6
10
7
10
10
8
Frequency [Hz]
77
Evolution of microelectronic technologies
Moore’s
No
roadmap,Law
room &
forMore
new ideas:
monolithic sensors, 3D integration
More than Moore: Diversification
Baseline CMOS: CPU, Memory, Logic
More Moore: Miniaturization
Analog/RF
HV
Power
Passives
Sensors
Actuators
Biochips
130nm
Interacting with people and environment
90nm
Non-digital content
System-in-package
(SiP)
Co
mb
65nm
45nm
32nm
22nm
Information
Processing
Digital content
System-on-chip
(SoC)
i ni
ng
So
Ca
nd
SiP
: H
ig h
e
rV
al u
eS
ys
tem
s
16 nm
.
.
.
V
Beyond CMOS
July 14, 2010
ITRS public conference – San Francisco
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
3
78
A further leap: 3D integration
The microelectronic industry has developed 3D integration of thinned and
bonded CMOS tiers with vertical interconnections through the silicon layers
as an alternative or complementary way to device scaling, with the goal of
enhancing memory capacity and microprocessor speed (by reducing length of
interconnections) and of improving the performance of image sensors (by
including pixel level high-speed signal processing).
The semiconductor detectors and front-end electronics communities in HEP and
photon science plan to take benefit from 3D integration for new pixel sensor
with advanced functionalities, smaller form factor, less material and dead
area, separation and optimization of sensing, analog and digital functions,…
New concepts may also be enabled by this technology.
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
3D vertical integration
•
•
•
•
A “3D” chip is generally referred to as a
chip comprised of 2 or more layers of
active semiconductor devices that have
been thinned, bonded and
interconnected to form a “monolithic”
circuit.
Often the layers (sometimes called
tiers) are fabricated in different
processes.
Industry is moving toward Vertical
Integration to improve circuit
performance.
– Reduce R, L, C for higher speed
– Reduce chip I/O pads
– Provide increased functionality
– Reduce interconnect power and
crosstalk
This is a major direction for the
semiconductor industry.
Optical In
Opto Electronics
and/or Voltage Regulation
Power In
Optical Out
Digital Layer
Analog Layer
50 um
Sensor Layer
Physicist’s Dream
Pixel control, CDS,
A/D conversion
Diode
Diode
Analog readout Analog readout
circuitry
circuitry
Diode
Diode
Digital
Analog
Sensor
Analog readout Analog readout
circuitry
circuitry
Conventional MAPS 4 Pixel Layout
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3D 4 Pixel Layout
80
Advantages of going 3D:
interconnections, delays and power
RAM, microprocessors, FPGAs,…
td  0.35 x rcl
2
Pavg = VDD x Iavg = Ctot x VDD
2
x fclk
Since C is mostly due to wiring:
Pavg  lavg
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
Two different approaches to 3D
integration for pixel sensors
“via first” process for 3D integrated circuits, where TSVs are drilled at the
foundry in the early stages of CMOS wafers processing. Very high density
interconnections (< 10 mm) are possible (VIPIX-INFN and 3D-IC consortium).
Tezzaron vias are very
small: Fvia=1.2 mm,
Flanding_pad=1.7 mm,
dmin=2.5 mm
Wafer bonding pads are
nominally on a 4 mm pitch
“via last” process for 3D integration of 2 layers
in heterogeneous technologies (CMOS chip + high
resistivity sensor), 4-side buttable device with low
density interconnections (pitch > 50 mm) in the
Valerio Re(AIDA
- V Scuola Nazionale
“Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
device periphery
project).
82
The experience of the 3D-IC consortium
The processing of 3D devices started about 3 years ago at
Tezzaron/GlobalFoundries and, after many technical problems, only recently fully
functional chips were delivered. This is a signature that these advanced 3D
technologies have not yet reached a full maturity.
Encouraging test results and a more effective user interface (MOSIS-CMP)
keep
alive the promise of achieving high performance 3D systems in our field.
INFN/IPHC
An example (INFN-VIPIX): a 3D
Deep N-Well MAPS with pixel
level time stamping and
sparsification on a 20 mm pitch.
s
S
NQ
HIT
D
FFSRK
DGND
CF
TIER 1
(BOTTOM)
D
KillMaskClk
AGND
Q
K
KillMaskIn
Q
CP
FFD
NQ
D
NQ
CP
FFDR
Q
R
CP
FFD
NQ
NHIT
Token
In
R
Vt
HIT
NHIT
D
KillMaskOut
5
5
5
Token
passing core
TokenOut
5
T_IN
T_O 5
time stamp
register
NRO_EN
ST RO_EN
Q
CP
FFD
NQ
TIER 2
(TOP)
ST RO_EN
Q
T_IN
T_O
time stamp
register
NRO_EN
pixel (7_5)
1
1st_LATCH
2nd_LATCH
0.8
Occupancy
NLatch
Enable
Inter-tier
bond pads
IFB
Token
passing core
GetY
DVDD
TimeStampOut
AVDD
GetX
discriminator
Time
Stamp
In
AVDD
CellClk
shaperless FE (SFE)
NMasterReset
Successfully tested,
communication between device
layers demonstrated.
0.6
0.4
5
0.2
0
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
355
360
365
370
VTH [mV]
375
380
3D readout integrated circuits interconnected to high
resistivity sensors:
standard bump bonding vs vertical integration
1st layer
Digital
section
Analog
section
Bump
bonding
Digital
section
2nd layer
detector layer
1st
layer
CuSn
bond
cross
section
Conventional solder bumps or more advanced, low
pitch CuSn bonding may still pose a problem for
low mass assemblies
Low-mass bonding of sensors to readout circuits
is possible with advanced high-density
interconnection technologies
Analog
section
2nd layer
Wafer
bonding
detector layer
Valerio Re - IV Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 11 – 15 aprile 2011
84
Exploiting 3D integration: the analog section of a 3D readout
chip for high resistivity pixels
Sensing
layer
Qd(t)
CF
Preamplifier
ANALOG
LAYER
Polarity
selector
CD
C2
Discriminator
VTH
Shaper
C1
+
PS
AVDD
AVDD
HIGH_GAIN
IF
INJ_CK
,
VFBK1
AGND
Pulser
INJ_EN
VFBK2
DATA_IN
Shift register
DATA_CK
HIT
Digital Threshold
Correction
B0
B1
B2
B3
D Q
D Q
D Q
D Q
MASK
In-pixel
logic
MASK INJ
D Q
D Q
DIGITAL
LAYER
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
85
Exploiting 3D integration: pixel-level logic with time-stamp
latch and comparator for a time-ordered readout
Valerio Re - IV Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 11 – 15 aprile 2011
Perspectives and support to 3D integration in the
semiconductor detector community
3D integrated circuits based on homogeneous layers (same CMOS technology)
and high density TSVs and interconnections remain a very promising approach
to advanced pixel detector readout and other applications.
The AIDA WP3 project is supporting the less aggressive “via
last” variant of 3D integration, where low-density TSVs are
etched in fully processed CMOS wafers. It is a mature
technology, presently available at various vendors.
This technique makes it possible to use heterogeneous
layers ( different technologies) for sensors and front-end
electronics and to fabricate four-side buttable devices with
minimal dead area.
A high-resistivity, fully depleted sensor can be combined in a low-mass assembly
with a readout chip designed in an aggressively scaled CMOS generation (usually not
available in the typical MAPS “Opto”processes), both with excellent radiation
hardness (among other properties).
Low-density peripheral TSVs can be used to reach
backside bonding pads for external connection. The
interconnection technology can be chosen according
to the pixel
pitch.
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
87
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
88
Conclusions
Front-end electronics for silicon trackers in future experiments is an
exciting challenge for integrated circuit designers
Classical analog problems (signal amplification and shaping, noise,
threshold dispersion) will require clever solutions
New industrial technologies (nanoscale CMOS, 3D integration, …) will be
exploited to achieve increasingly demanding specifications
3D integration is progressing in the microelectronic industry, and we
have to be ready to exploit it. Ultimately, it may allow designers to
avoid using sub-50 nm processes for analog and digital circuits in very
small pixel readout cells.
R&D activities in these technologies have to be supported by our
community, since they enable new concepts for detector systems.
AIDA WP3 is doing this for 65nm CMOS (with CERN support) and
for 3D integration.
Technology watch for novel devices and processes has to continue,
since the evolution of microelectronics is not going to end soon.
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
89
References
E. Gatti, P.F. Manfredi: “Processing the signals from solid-state
detectors in elementary-particle physics”, La Rivista del Nuovo
Cimento, 1986
V. Radeka: “Low-noise techniques in detectors”, Ann. Rev. Nucl. Part.
Sci., 1988
G. Lutz: “Semiconductor radiation detectors”
L. Rossi, P. Fischer, T. Rohe, N. Wermes: “Pixel Detectors. From
Fundamentals to Applications”
H. Spieler: “Semiconductor detector systems”
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
90
Backup slides
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
91
Pixel detectors in future HEP experiments
• Physics goals set severe requirements:
– High granularity  small pixel pitch
– Low material budget  low mass cooling, thin silicon wafers, small
amount of material for support and interconnections
– Small distance to interaction point  large background
High data rate,
Level 1 trigger
In MAPS, loss of
efficiency due to inpixel PMOS
Full CMOS
radiation hardness
(deep submicron CMOS
intrinsically rad-hard)
Data sparsification
Mixed-signal chips
Digital-to-analog
interferences
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
92
Time stamp readout in pixel readout chips
A time stamp counter generates a time reference.
The time stamp code:
1) can be distributed to all pixels
The content of an in-pixel time stamp register is frozen
when the pixel detects a hit and is then transmitted to the
periphery.
2) can stay in the chip periphery or in the “end-of-column”
control logic block.
When a pixel is hit, the end-of-column or periphery logic is
informed that one or more hits have occurred and stores
the relevant time stamp in a register.
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
93
Effect of noise on discriminator firing efficiency
1
Noiseless system
Q
Qth
Q
Q
P Q th  


Qth
0
Qth
Q
Effect of noise
Qth
 q  Q 2 
1

 
1 
Q  Q th 
exp 
dq

1

Erf



2 
 2 
2Q
2



2

Q 
Q th
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
Q
94
Analog channels (FSSR2 chip)
Preamplifier
Programmable Gain
Cf1
Programmable
Baseline
Restorer
Cf
Bias
+
Gf
CD
CAC
Hit/NoHit Discriminator
Threshold
circuit
Shaper
CR-(RC)2
To 3-bit Flash ADC
BLR
Single-ended/
Differential
conversion
Comparator
Vth
-
Kill
+
Cinj
Test Input
(from Internal
Pulser)
Programmable
Peaking time
Threshold DAC
(chip wide)
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
95
Processing the signal from the sensor:
the baseline restorer
Since the signal at the preamplifier output is not an ideal voltage
step, but returns to baseline with a long time constant, the signal at
the shaper output has a long tail. This results in a baseline shift at
the discriminator input, with related statistical fluctuations, adding
to the threshold dispersion.
Channel 1, t =85 ns
Channel 2, t =85 ns
p
p
100
Comparator firing efficiency (%)
Comparator firing efficiency (%)
100
without baseline shift
1% occupancy
2% occupancy
80
60
40
20
60
40
20
0
0
0.6
without baseline shift
1% occupancy
2% occupancy
80
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
Injected charge [fC]
Input signal discriminator scan without BLR
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
Injected charge [fC]
Input signal discriminator scan with BLR
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
96
Shift and fluctuations of the baseline at the discriminator
input can be removed by a baseline restorer.
0
shaper output
-0.05
OUT
(V)
BLR output
V
t = 85 ns
P
-0.1
High gain setting
-0.15
0
0.5
1
1.5
2
2.5
3
Time (ms)
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
97
Pixel Unit Cell
Column
Bus
3 bit FADC
Vdda
Amplifier
Ifb
+
Binary Encoder
& Register
Vth7
Token
Out
Vfb2
Vff
Vth2
Sensor
Pulse ht: [0:2]
Inject
Test
Vref
Vth1
Hit
Bias voltages &
currents are set by
DAC’s.
Vth0
Command
Interpreter
4 pairs of lines,
4 commands each:
Latch Data
Output Data
Idle
Reset
Token
& Bus
Controller
Row #
[0:7]
Token
In
Kill
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
98
FNAL idea,
implemented by
INFN in a 130nm
CMOS MAPS
Cell CK
4
X=1
Cell (1,1) gXb
First
token in
4
Y=1
Tkin Tkout
1
gYb
TS
Tkout Tkin
Y=2
1
Last token
out
4
Y=16
Readout CK
4
X
4
Y
MUX
5
T
5 Time
Stamp
Buffer 1
1
5
1
gYb
4
X=2
Cell (1,2) gXb
TS
Cell (2,1) gXb
4
ILC VTX pixel readout architecture
TS
Tkin
Tkout
gYb
Cell (2,2) gXb
TS
Tkout Tkin
gYb
Readout phase:
• token is sent
Serial data
output
5
1
5
Time
Stamp
Buffer 2
• token scans the matrix and
4
X=16
Cell (1,16)gXb
Hit
pixel
TS
Tkin Tkout
gYb
Cell (2,16)gXb
gYb
Cell (16,16)
gXb
TS
TS
TS
gYb
gYb
Stamp
• the
Buffer 16
1
5
pixel points to the
X and Y registers at
the periphery and
gXb=get_X_bus
• sends off the time
content
gYb=get_Y_bus
stamp register
TS=Time_Stamp
• data are serialized and
ahead
Tkin=token_in
token scans
Tkout=Token_out
TS
Cell (16,2)gXb
Tkout Tkin
• gets caught by the first
Timehit pixel
Tkout Tkin
Cell (16,1)gXb
Tkout Tkin
5
Tkout Tkin
The number of elements
may be increased without
changing the pixel logic
(just larger X- and Yregisters and serializer
will be required)
gYb
Valerio Re - V Scuola Nazionale “Rivelatori ed Elettronica”, INFN – LNL, 15 – 19 aprile 2013
99