Transcript Design and Simulation of novel Dual

Silicon on Insulator MOSFET
Technology:
Design and Evolution of the Modern SOI
Fully-depleted MOSFET
Presented By:
Aniket A. Breed/ Dr. Marc Cahay
Department of Electrical and Computer Engineering and
Computer Science.
Semiconductor Devices Laboratory
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SOI – The technology of the future.
Welcome to the world of Silicon On Insulator
Highlights
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Reduced junction capacitance.
Absence of latchup.
Ease in scaling (buried oxide need not
be scaled).
Compatible with conventional Silicon
processing.
Sometimes requires fewer steps to
fabricate.
Reduced leakage.
Improvement in the soft error rate.
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Drawbacks
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Drain Current Overshoot.
Kink effect
Thickness control (fully depleted
operation).
Surface states.
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The Metal Oxide Semiconductor Field-Effect Transistor
(MOSFET)
In layman terms, MOSFET acts like a
switch
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A Historical Perspective
Moore’s Law
• Number of Transistors on an integrated circuit
chip doubles every 1.5 years.
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(Courtesy: Intel© Corporation)
Motivation
• Silicon-only planar transistors are
fast approaching their scaling limit.
• Short channel effects limiting scaling
into sub nanometer regime.
• Oxide thickness cannot be scaled
down further, problems of tunneling.
• Need to keep Silicon technology as
the base technology while innovating
future devices; cost is an important
factor.
• Performance and power dissipation
need to be improved.
• Smaller is faster !!
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MOSFET Scaling Trends
Courtesy: Hewlett-Packard Labs
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Planar MOSFET Scaling (Short-Channel Effect)
Lg = 0.35 m, Tox = 8 nm
Lg = 0.18 m, Tox = 4.5 nm
Short-Channel Effect
Short-Channel Effect
Lg = 0.10 m, Tox = 2.5 nm
Lg = 0.07 m, Tox = 1.9 nm
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What After the Planar MOSFET (Alternative Approaches)
Strained Silicon Approach
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Silicon grown on a layer of relaxed
material like SiGe which has a near
similar lattice constant as that of
Silicon.
Strain induced in Silicon results in an
improvement in the mobility, hence
results in faster devices.
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Silicon-on-Insulator (SOI) Approach
 Silicon channel layer grown on a
layer of oxide.
 Absence of junction capacitance
makes this an attractive option.
 Low leakage currents and compatible
fabrication technology.
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Classification of SOI MOSFETs
Conventional MOSFET
Partially depleted SOI
MOSFET
Fully depleted SOI
MOSFET
• Silicon film thickness greater than bulk depletion width for a partially-depleted MOSFET
and less than the gate depletion width for a fully-depleted MOSFET.
• Partially depleted MOSFETs often plagued by KINK effects, fully depleted devices
virtually free from such effects.
• Partially depleted devices can be faster than fully depleted devices under certain
operating conditions.
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Illustration of the “Kink” effect (Partially depleted
structures)
Partially depleted MOSFET
Fully depleted MOSFET
Kink effect is an intricate, yet undesirable phenomenon.
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Why Multi-Gate SOI MOSFETs ?
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Higher current drive  better performance
Prophesized to show higher tolerance to scaling.
Better integration feasibility, raised source-drain structure, ease in integration.
Larger number of parameters to tailor device performance
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IBMs FinFET / Double-Gate SOI (Nanoscale Device Research
Group)
Courtesy: IBM T.J. Watson Research Center, Yorktown Heights, NY
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UC Berkeley Results – FinFET/ Double Gate (2000-04)
Gate Length = 30nm, Oxide thickness =2.1nm
Gate Length = 30nm, Fin
Width =20nm
Gate Length = 20nm
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INTEL’s TriGate SOI (SSDM 2002)
Highest ever performance reported for NMOS and PMOS devices on a single
substrate !!
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INTEL TriGate Results (2002- till date)
LG = 15nm
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LG = 60nm, TSi = 36nm and WSi = 55nm
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TSMC’s -gate Device (SSDM-2002)
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Research Work at TSMC (2002)
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Multi-Body Single-Gate Devices
Front-View
Body
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• Multi-Body Single gate
devices an attractive option.
• Increased current drive
using a single gate.
• Total current nearly equals
the current thru one body
multiplied by the number of
body regions.
• Fabrication feasibility.
• Feasible for the Dual-Gate,
Tri-Gate and -gate
devices.
Top-View
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Device Design (A brief Summary)
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Research Initiative
Devices under investigation completely novel.
Only N-channel devices investigated to some extent.
Device structural variations and their effect on performance investigated to
a minor degree.
Microwave performance of the device’s not investigated at all.
Modeling Approach at U.C. (Semiconductor Devices Laboratory)
Numerical device simulators from SILVACO International and ISE.
Extensive 3-D modeling of the four N-channel device structures.
P-channel devices to be modeled in succession.
RF analysis of the N-channel devices followed by the P-channel devices,
extraction of important device parameters.
Effect of temperature variation on device performance to be analyzed.
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Preliminary
Results and Future Work
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Multi-Gate SOI MOSFETs (3-D Views)
TriGate
Double Gate/
FinFET
-Gate
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QuadGate
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Multi-Gate SOI MOSFETs (2-D Cutplane Views)
Double-gate/
FinFET
TriGate
-Gate
QuadGate
Note: Symmetric and Asymmetric devices possible
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The -Gate Transistor (The Pseudo 4th gate)
• Physics of operation difficult to
understand.
• Lies somewhere in between a TriGate and a Quadruple-gate device
as regards structure.
• Virtual presence of a back-gate in
oxide layer that acts as a pseudofourth gate.
Virtual Back Gate
• Presence of the virtual gate
prevents electric field lines from
the drain from penetrating the
channel.
• Amount of vertical gate polysilicon
penetration a design factor.
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PiGate Transistor (Vertical Gate Penetration Simulation)
Baseline device dimensions
Gate Length = 50 nm
Body Width = 50 nm
Body Height = 50 nm
Channel Doping = 1x1016 /cm3
Source/ Drain Doping = 1x1019 /cm3
Oxide Thickness = 2 nm
Gate Workfunction = 4.6 eV
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N-type devices considered.
50-100nm technology node well developed
and has translated into a manufacturable
technology.
Too shallow or too deep an etch in the oxide
necessitates accuracy and also poses stringent
fabrication tolerances.
Optimum value of 50 nm chosen as the
vertical polysilicon penetration depth.
Drain-Current (ID - VDS) Characteristics
FinFET
TriGate
PiGate
QuadGate
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Gate (ID - VGS) Characteristics (FinFET and TriGate)
FinFET Device Characteristics
Threshold Voltage = 0.196 V
Subthreshold Slope = 72 mV/decade
Off Current = 70 A/m
DIBL = 64.67 mV/V
TriGate Device Characteristics
Threshold Voltage = 0.179 V
Subthreshold Slope = 84 mV/decade
Off Current = 37.09 A/m
DIBL = 75.11 mV/V
FinFET
TriGate
Omega-Gate
Quadruple-Gate
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Gate (ID - VGS) Characteristics (-gate and Quadruple-gate)
-Gate Device Characteristics
Threshold Voltage = 0.193 V
Subthreshold Slope = 68.08 mV/decade
Off Current = 55.82 A/m
DIBL = 134.9 mV/V
FinFET
TriGate
Omega-Gate
Quadruple-Gate
Quadruple-Gate Device
Characteristics
Threshold Voltage = 0.198 V
Subthreshold Slope = 65 mV/decade
Off Current = 50 A/m
DIBL = 100.74 mV/V
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Device Structural Variations (Gate Length)
FinFET
TriGate
-Gate
Quad-Gate
J-T. Park and J-P Colinge, IEEE Transactions on Electron Devices, pp.
2222-2228, vol. 49, no. 12, Dec. 2002.
Device Dimensions
Fin Width = 50 nm
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Subthreshold Slope = 70-80 mV/decade and lower for
switching applications.
Number of gates does influence device operation.
Channel Doping = 1x 1016 /cm3
Workfunction = 4.6 eV
Oxide Thickness = 2 nm
A. Breed and K.P. Roenker, pp. 150-151, International Semiconductor Device Research Symposium, 2001.
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Device Structural Variations (Channel Doping)
FinFET
TriGate
-Gate
Quad-Gate
J-T. Park and J-P Colinge, IEEE Transactions on Electron Devices, pp.
2222-2228, vol. 49, no. 12, Dec. 2002.
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Near identical behavior in both graphs.
Channel doping normally maintained at a low value to
minimize effects of scattering.
Mobility degradation observed at high values of channel
doping.
Moderate levels of channel doping could be used.
Device Dimensions
Fin Height/Width = 50 nm
Gate Length = 50 nm
Workfunction = 4.6 eV
Oxide Thickness = 2 nm
A. Breed and K.P. Roenker, pp. 150-151, International Semiconductor Device Research Symposium, 2001.
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Device Structural Variations
(Gate Length and Channel Doping)
FinFET
TriGate
-Gate
Quad-Gate
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Threshold voltage decreases with decrease in gate length,
short-channel effect seen to exist in these devices.
Threshold voltage sensitive to channel doping beyond 1x10 16
/cm3.
Can we use channel doping to tailor threshold voltage?
Device Dimensions
Fin Height = 50 nm
Fin Height = 50 nm
Workfunction = 4.6 eV
Oxide Thickness = 2 nm
A. Breed and K.P. Roenker, pp. 150-151, International Semiconductor Device Research Symposium, 2001.
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Device Dimension Variations
(Fin Height)
FinFET
TriGate
-Gate
Quad-Gate
Device Dimensions
Gate Length = 50 nm
Channel Doping = 1x1016 /cm3
Workfunction = 4.6 eV
Oxide Thickness = 2 nm
Fin Width = 50 nm
A. Breed and K.P. Roenker, pp. 150-151, International Semiconductor Device Research Symposium, 2001.
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Device Dimension Variations
(Fin Width)
FinFET
TriGate
-Gate
Quad-Gate
Device Dimensions
Gate Length = 50 nm
Channel Doping = 1x1016 /cm3
Workfunction = 4.6 eV
Oxide Thickness = 2 nm
Fin Height = 50 nm
A. Breed and K.P. Roenker, pp. 150-151, International Semiconductor Device Research Symposium, 2001.
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Device Design Parameters
FinFET
TriGate
-Gate
Quad-Gate
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Important step in device design is not patterning of gate region ,
but instead it is the patterning of the body width.
Ideally increase in the number of gates provides an improvement in
performance.
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Device Dimensions
Workfunction = 4.6 eV
Oxide thickness = 2 nm
Device Design Parameters (..cont.)
FinFET
TriGate
-Gate
Quad-Gate
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TriGate variation minimal when Fin Width is considered.
– Ideal Gate Length/ Fin Width ratio for FinFET is 1.3 or higher, for a TriGate is
unity or higher, for a -gate it is 0.8 or higher and for a Quadruple-gate it is 0.6 or
higher.
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Effect of Variation in Gate Oxide Thickness
FinFET
Device Dimensions
TriGate
Channel Doping = 1x1016 /cm3
Fin Width = 50 nm
Fin Height = 50 nm
Gate Length = 50 nm
Gate Workfunction = 4.6 eV
-Gate
QuadGate
• Thinner oxides with higher dielectric constants
could be looked upon as an alternative for either
device. (Hints at the need to look into new
materials (HfO2, ZrO2) as a substitute for SiO2 in
nanoscale devices).
A. Breed and K.P. Roenker, pp. 150-151, International Semiconductor Device Research Symposium, 2001.
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MOSFET Microwave Performance
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Silicon-only planar MOSFETs are under consideration.
Devices below 200nm gate length are experimental devices.
All devices can be optimized for either a larger cut-off frequency or a larger
maximum frequency of operation.
No strained technology used for MOSFET fabrication.
Juin J. Liou and Frank Schwierz, Solid State Electronics, pp. 1881-1895, vol. 47, 2003.
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Current Gain (h21) & Unilateral Power Gain (UMax)
FinFET
Gate Bias = 0.8 Volts
TriGate
TriGate
TriGate
FinFET
FinFET
Legend
  Current Gain
  Unilateral Power Gain
 Identical behavior for the FinFET and TriGate
transistors.
 TriGate performance again superior to the
FinFET.
 Overall device performance better than that of a
planar MOSFET !!
A. Breed and K.P. Roenker, IEEE Conference on Silicon Monolithic Integrated Circuits in RF Systems, Atlanta, GA 2001.
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Variation in the Cutoff Frequency (fT)
Gate Bias = 0.8 Volts
TriGate
TriGate
FinFET
FinFET
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Similar variation of fT with gate bias and frequency exhibited by the FinFET and TriGate
transistors.
TriGate exhibits a peak value of 51.5 GHz and the FinFET a peak value of 42.2 GHz for
the cut-off frequency.
TriGate is superior again compared to the FinFET (nearly a 20% improvement)!!
Values however less than that reported for an optimized planar RF MOSFET transistor
(178 GHz - J-J. Liou et. al, Solid State Elec., vol. 47, 1881-1895, 2003).
A. Breed and K.P. Roenker, IEEE Conference on Silicon Monolithic Integrated Circuits in RF Systems, Atlanta, GA 2001.
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Variation in the Maximum Frequency of Oscillation (FMax)
Gate Bias = 0.8 Volts
TriGate
TriGate
FinFET
FinFET
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Similar variation of fMax with gate bias and frequency exhibited by the FinFET and
TriGate transistors.
TriGate exhibits a peak value of 228 GHz and the FinFET a peak value of 183 GHz.
TriGate is superior again compared to the FinFET (20% improvement)!!
TriGate performs even better than a planar RF transistor (193 GHz - J-J. Liou et.
al, Solid State Elec., vol. 47, 1881-1895, 2003) !!
A. Breed and K.P. Roenker, IEEE Conference on Silicon Monolithic Integrated Circuits in RF Systems, Atlanta, GA 2001.
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Conclusions and Future Work
Conclusions:
• Successfully modeled devices in 3-dimensions.
• Understood device design space and scaling constraints.
• Undertook a study to understand fabrication tolerances to which every
device could be exposed.
• Both subthreshold and RF performance explored.
Future Work:
• Model p-channel devices, scaling rules could differ.
• Understand device design in totality given a variation in two or more than
two parameters.
• Investigate their Microwave characteristics.
• Comparison with n-channel performance for CMOS and BiCMOS
incorporation.
• Understand effects of temperature on device performance.
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References
1.
A. Breed and K.P. Roenker, “Dual-gate (FinFET) and
TriGate MOSFETs: Simulation and design,” Proceedings of
the International Semiconductor Device Research
Symposium (ISDRS-2003), pp. 150-151, December 2003.
2.
J-T. Park and J-P Colinge, “Multiple-Gate SOI MOSFETs:
Device Design Guidelines,” IEEE Transactions on Electron
Devices, pp. 2222-2228, vol. 49, no. 12, Dec. 2002.
3.
Aniket Breed and Kenneth P. Roenker, “A Small-signal, RF
Simulation Study of Multiple-gate MOSFET Devices,”
IEEE Topical Meeting on Silicon Monolithic ICs in RF
Systems, Atlanta, GA, Sept. 2004.
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