Transcript 3-Dimensional IC Fabrication

3-Dimensional
IC Fabrication
Dominic DelVecchio
Bradley Hensel
Outline
•
•
•
•
•
•
•
•
What is 3D IC?
Why?
Theoretical Process
Benefits
Technical Challenges
Conclusion
References
Concepts
What is 3D IC?
3D IC fabrication is a process that involves
building transistors on an IC chip in such a
way that you have a vertical structure instead
of a simple 2D structure.
Why 3D Fabrication?
As transistors grow smaller and smaller to fit more on a
wafer, the precision of equipment needed to reliably
manufacture IC chips grows vastly in cost. Currently we
are at a point where the cost to manufacture smaller
transistors into an 2D IC chip is not economical in any
regard. Thus IC chip manufacturers have begun to
produce 3D structures on wafers allowing for more
transistors per chip without the incurred cost of
nanofabrication level machinery. This trade off for more
transistors in the vertical as compared with the horizontal
comes with both great benefits and challenges.
3D IC Fabrication
1. A crystalline structure such as another silicon wafer must
be place on top of the first circuit level and joined
through the process of plasma-activated lower
temperature wafer bonding. Seeded Crystallization may
also be used.
3D IC Fabrication
2. Construction of the second or above layers on an IC is
accomplished through a process of laser annealing.
Laser annealing as opposed to more conventional
methods allow for the first circuitry layer to remain at
almost room temperature while the second or above
layer gets hot enough to perform the needed fabrication
steps. This is extremely useful as you will not negatively
affect the doping concentrations of previous layers.
Completed (2 layer) IC
Benefits (Power and Bandwidth)
3D fabrication allows circuit components to be
located physically closer to each other. This
allows circuits to operate with less power
consumption and at a higher bandwidth - two
qualities that are of utmost importance in
today's technology (especially in memory).
Benefits (Cost and Material Type)
By producing layers individually and testing
before combining them, cost can be reduced.
If a layer is defective, only that portion of the
circuit is discarded and not the entire unit.
Furthermore, layers can be produced of
different semiconductor materials to combine
the benefits of various materials into the
same chip
Benefits Summary
•
•
•
•
Reduced power consumption
Reduced cost
Higher bandwidth over many components
Ability to combine materials
ALSO (extrapolating from these benefits)
•
•
Reduced footprint
Greater design flexibility
Technical Challenges
(Heat)
In shifting from a planar to a volumetric
structure, heat buildup inside becomes an
issue.
To mitigate this issue, heat must be considered
in the design phase and kept to the outside of
the structure.
Technical Challenges
(Yield)
Producing the 3D chips requires more manufacturing steps
than producing 2D chips. Since some units are
generally lost at each step, yield may be reduced.
Contamination between layers is much more severe than
standard 2D chip contamination
Alignment, imagine trying to align something in the
nanometers of length...one mistake and it's all over
Layered testing may help offset yield related issues.
Technical Challenges
(Design Complexity)
3D chips are inherently more complex and
difficult to visualize, and are thus more
difficult to design for.
3D CAD tools need to be developed to make
the design process manageable and
economic.
Technical Challenges
(Wire Density)
Current processes state the interlevel
interconnect density of 3D circuits obtained
by aligned bonding of pre-fabricated circuit
levels is currently limited to about 10^6
wires/mm^2
With more advanced, in development,
processes such as the one described above
can reach well into the millions of
wires/mm^2
Conclusion
Massive benefits are to be had from 3D IC
chips, however many challenges must be
overcome to employ 3D fabrication
processes on a large scale, in more than the
currently limited industries.
It's likely that 3D IC production will serve an
important role in memory and cache memory
based applications in the near future.
References
Rajendran, Bipin. "Sequential 3D IC Fabrication – Challenges and Prospects."
Chomsky Stanford. Department of Electrical Engineering, Stanford University, n.d.
Web. 27 Apr. 2013.
<http://chomsky.stanford.edu/data/bipin/VMIC_Rajendran_06.pdf>.
Patti, Robert. "Impact of Wafer-Level 3D Stacking on the Yield of ICs." Future Fab
International. Tezzaron Semiconductor, 07 Sept. 2007. Web. 27 Apr. 2013.
<http://www.future-fab.com/documents.asp?d_ID=4415>.
"EDA's Big Three Unready for 3D Chip Packaging." EDA's Big Three Unready for 3D
Chip Packaging. EE Times, n.d. Web. 27 Apr. 2013.
Dally, William J. "Future Directions for On-Chip Interconnection Networks." OCIN
Workshop. 7 Dec. 2006. Web.
Concepts
Main Concepts:
1. Not economical to build smaller?, build vertical.
2. Designing in 3D is inherently more difficult, and new
software needs to be developed
3. Lower yield process due to complexity and vulnerability
between layers.
4. Higher bandwidth capability due to reduced
interconnection length.
5. Temperature considerations must be dealt with.