Transcript High Rho CMOS sims

Friday, May 13th 2016
Simulation of High Resistivity (CMOS)
Pixels
Stefan Lauxtermann, Kadri Vural
Sensor Creations Inc.
AIDA-2020 CMOS Simulation Workshop
May 13th 2016
Friday, May 13th 2016
OUTLINE
1.
Definition of High Resistivity Pixel
• Also referred to as Deep Depletion (DD) or Fully Depleted (FD) Pixel
2.
Challenges of High Resistivity Pixels
• Parasitic Bipolar Transistors
3.
Advantages of High Resistivity Pixels
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Broad Spectral Sensitivity
High Snapshot shutter Efficiency
Nanosecond exposure time control
High radiation tolerance
Summary
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Friday, May 13th 2016
What is a Monolithic Deep Depletion
(DD) CMOS Image Sensor (CIS)?
Standard CIS (color)
NMOS transistor
Pixel
Color Filter
Micro lenses
Deep Depletion CIS
Photodiode
Passivation layer
(e.g. HfO2)
Pixel
Electrical
drift field
Only backside illuminated
devices considered
Deep Depletion CMOS Sensors have Thicker Active
Absorption Region Than Standard CIS
V
Backside
Electrode
AR Coating
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Comparison of Standard versus
Deep Depletion CMOS Sensor
Standard CIS
Deep Depletion CIS
Fabrication Process CMOS
CMOS with modifications
Pixel Circuitry
NMOS or PMOS (but not both)
NMOS + PMOS
Material Resistivity
<10 Ohm x cm
>1 kOhm x cm
Sensor Thickness
< 10micron
> 10micron
Charge Collection
Diffusion
Drift
Backside Electrode
No
Yes (unless EPI with build in field)
Main application
Visible cameras (mostly consumer)
UV–NIR cameras (scientific, industrial)
Photo Sensor
Pinned Photodiode
PIN Photodiode
Main Pixel Type
4T
3T (or derivative)
Minimum pixel pitch 1 micron
4 micron
Dark Current (typ. @RT) <10pA/cm2
> 100pA/cm2 (depending on thickness)
Optoelectronic Performance of DD-CMOS Comparable to DD-CCDs
(although not demonstrated in single CMOS device yet)
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Comparison of Deep Depletion
CMOS Technologies
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hybrid FPA
(not monolithic)
3D-IC
(pseudo monolithic)
Custom EPI layer
(no backside contact)
Optimum Performance
Lowest Manufacturing Cost
Least Developed
Very few products
monolithic DD CMOS
using high rho silicon
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Friday, May 13th 2016
SCI’s Deep Depletion CMOS
Technology Well Structure
0V
NMOS
PMOS
PD
Deep Pwell
N--
substrate
+
-
30 – 500µm
-Vback
• Deep P-well required to isolate circuitry from High Resistivity Silicon
• Electrons are collected by lateral and vertical drift fields.
Deep Depletion Sensor is 3D structure with vertical and
lateral Parasitic Bipolar Transistors
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Friday, May 13th 2016
Electrostatic Potential in Thick
Photodiodes with Backside Bias
N Implant regions
front side
0 mm
thickness
Standard
Silicon
100 mm
3.4V
High Rho
Silicon
-10.4V
back side
100 mm
thickness
0 mm
100 mm
thickness
0 mm
Deep Photo
Sensitive Region
can only be
Created in High
Resistivity Silicon
thickness
-10 V
Light
absorbed in
grey region
cannot be
detected
3V
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CMOS IC’s on High Resistivity
Silicon More Prone to Latch-Up
PMOS
NMOS
RNWELL
RNsub
+
RPWELL
N-- substrate
• Latch up Tendency increases with
– Increasing RNsub
– Decreasing C
– Increasing Q
Parameters are worse in high rho Si compared to standard Si
High resistivity Silicon Sensor IC Require Strong
Substrate Connections to Minimize Latch-Up
Probability
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Friday, May 13th 2016
Parasitic Bipolar Transistors on
High Resistivity Silicon
0V
PD
NMOS
Deep Pwell
PMOS
Horizontal NPN
N-- substrate
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Horizontal NPN
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Vertical PNP
PD
Vertical
PNP
30 – 500µm
-V
– Risk of high current path between neighboring photodiodes back
– Risk of high current path between front side Deep P-Well and backside electrode
Firing of horizontal or vertical can significantly
decrease sensor performance and must be avoided
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Friday, May 13th 2016
Bipolar Transistors can be Completely
Suppressed by Introducing an Extra
Deep Nwell Implant
vssDPW
GND
vssDNW
• Deep Pwell can be biased below GND
• Parasitic transistor is turned off
November 19, 2015
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Friday, May 13th 2016
High Rho CIS Process Flow (Front Side)
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Preparation of 8’’ wafers for CMOS fabrication
Implantation of deep P wells
Standard CMOS IC fabrication
Wafer thinning and polishing
Deposition of Backside electrode
Simulated implantation profile
Deposition of AR coating
Singulation of fully processed thinned CMOS wafers into individual chips
Packaging
DD CIS Fabrication Requires some
Modifications to Baseline CMOS Process
Plus Backside Post Process
Thin film simulation of AR coating
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Shallow Implantation + Laser
Anneal on Back Side
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Measured
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implantation
profiles for
different laser
light fluences •
Simulations are based on beam line
implantation + furnace anneal
All curves have the same implant
energy and dosage:
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1keV (minimum possible with simulator)
1E15at/cm2
Anneal
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None (As implanted)
900C/1sec
900C/10sec
For very shallow implants the profile
is defined by annealing, not the
implantation energy
Profiles not well simulated
with conventional beam line
simulation approach followed
by furnace anneal
January 28, 2016
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Friday, May 13th 2016
3D Simulation of High Rho CMOS Pixel
15mm pixel
pitch
Cut plane
Cut line
Potential [V]
3.5
Potential [V]
50mm
3.5
-10.5
50mm thick Si
-10.5
Backside Contact
Backside illumination
3D Device Simulations are necessary especially for small pixels
September16, 2014
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Friday, May 13th 2016
Absorption of Light in Silicon
Photo-generated
charge cannot be
collected when
generated in first
~0.1um of silicon
Maximum depth for CMOS
process boron and phosphorus
implants
Near InfraRed (NIR)
Ultra Violet (UV)
• Most commercial CMOS sensors operate in visible domain
High Resistivity Silicon Sensors Provide Benefits in
Detection of Light Outside the Visible Domain
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Friday, May 13th 2016
Comparison of Quantum Efficiency
for Various Silicon Sensors
Deep depletion sensor
with broadband AR
coating
Thick
Backside
Illuminated
Sensor
Backside illuminated
deep depletion sensor
Front Illuminated
Photodiode sensor
(curves are generic
not measured on DD-CMOS sensor)
DD-CMOS Can Achieve QE of Best Scientific Silicon Sensors
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Friday, May 13th 2016
Snapshot Shutter in Backside
Illuminated Image Sensors
Standard Silicon
Photodiode
High Rho Silicon
Shutter transistor
Storage Node (SN)
Electronic shield
around SN
• Photons can reach SN
• Without charge
amplification extinction
ratio limited to <70dB
• Photons are absorbed in
thick active silicon region
before reaching SN
Backside Illuminated Image Sensor
on 50 µm thick High Rho Silicon
Achieves Extinction Ratio >120dB
for   640nm without amplification
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Nano Second Imaging
N
V
Front side
N implant
collection node
I
High rho substrate
(Intrinsic silicon)
P
Back side
P implant
electrode
Sensor in high rho imager
is a PIN photodiode
Transit time of photo generated charge carriers in 100um FD CMOS imager with 100V
backside bias < 1nsec, corresponding to a 3dB bandwidth > 1GHz
Fully Depleted Imager on Intrinsic Silicon is Suited
to Support Nanosecond Integration Time Windows
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Friday, May 13th 2016
Dark Current on 50um Thick Silicon
measured
value
Diode current is not zero at 0.0V
Transition bias point shifted due to charge
injection from backside electrode
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Measured on 1mm2 large test pixel arrays, on wafer level, at room temperature
1V back bias was applied
Measured Dark Current is Close to Predicted Depletion Current of <1nA/cm2 at RT
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Friday, May 13th 2016
Increased Tolerance to Radiation
Induced Displacement Damage
Published by Tomasz
Hemperek CPIX 2014
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Irradiation by heavy particles (proton, neutron) removes Si atoms from crystal lattice
– Also referred to as Non Ionizing Energy Loss
– Causes highly localized centers of leakage currents in imagers
– Different from Ionizing Energy Loss through X- and -rays → Charge deposition in SiO2
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No good design counter measures available against Displacement Damage (DD)
– CMOS IC’s can be hardened against X- and -rays by design
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Effect of displacement damage can be kept isolated in high rho silicon
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Efficient charge collection can be maintained if detector bias can increased through accumulation of damage
Requires independent substrate bias control
Thick High Rho Silicon Sensors Suited for Operation
up to Very High Flux Levels <1016 neq/cm2
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Summary
• High rho CMOS pixels offer unique performance not
achievable by any other sensor technology
• Front side processing compatible with capabilities of
standard CMOS fabrication facilities
– Some modifications of standard recipes required
– New Process Design Kit (PDK) must be developed
• Backside processing mandatory to utilize all advantages
– CMOS circuits on front side limit temperature of backside process
• Very few high rho sensor products currently available
– Most high rho sensor chips are custom developments
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Friday, May 13th 2016
Thank You for your attention!
Friday, May 13th 2016
About Sensor Creations, Inc. (SCI)
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Founded by Stefan Lauxtermann in 2010
Located in Southern California
Affordable, ROIC and image sensor design
– Design (in house)
– Fabrication (through CMOS fab partner)
– Test (in house)
– Prototype and low volume packaging (in house)
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Extensive suite of silicon proven IP blocks available today
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Low noise snapshot shutter pixels with multi frame storage
Low noise readout chain programmable
Serial interface (SPI)
14bit high speed, low power column parallel ADC (measured)
– High speed I/O port with 1Gbit/sec (measured)
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Fully depleted backside illuminated CMOS imagers
– Custom designs
– Products
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Prototype Cameras
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Friday, May 13th 2016
Absorption of Minimum Ionizing
Particles (MIP) in Si
Electron hole pair
generation per micron of
absorbing Si according to
Bethe-Bloch calculation of
mean energy loss of
charged particles in Si
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Generated Electron-Hole pairs can only be detected if they are separated by an electric field
– Such as the electric field in the depletion region of a high resistivity sensor
MIP Detector on High Resistivity Silicon Provides Maximum
Detection Efficiency with the least Amount of Material in Beam Path
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Friday, May 13th 2016
Absorption of Soft X-Rays in Si
Absorption length of soft
X-Rays in Silicon
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For direct X-ray detection active Si region must be thicker than possible in low rho Si
Front to backside PIN (P-type – Insulator N-type Si) diode used in high rho CMOS sensor
Upper energy limit for direct X-ray imaging determined by scattering – not limited absorption
Monolithic CMOS Detectors on High Resistivity Silicon are Suited for
Direct Image Detection of Soft X-Rays up to ~30keV
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