Transcript ee222-lect1x

EE222 Winter 2013
Sung Mo (Steve) Kang
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Office BE235
Phone 831-459-3580
Cell 831-706-5456Office BE23531-459-3580
[email protected]
References
• Main: Jan Rabaey, Low Power Design Essentials, Springer, 2009
• Others:
– A. P. Chandrakasan, et al., Low Power CMOS Digital Design,
Kluwer Academic Publishers,1995
– ITRS 2011 ( http://www.itrs.net)
– R. Sarpeshkar, Ultra Low Power Bioelecrronics, Cambridge Univ.
Press, 2010
– F. Catthoor, Unified Low Power Design Flow, Kluwer Academic
Publishers, 2000
– Selected articles in journals and conferences
Lecture No.
Date
Subject
Reference
1
Jan 8 (T)
Introduction
Rby-Ch1
2
Jan 10 (Th)
Power, Energy Basics
Rby-Ch3
3
Jan 15 (T)
Circuit level power optimization
Rby-Ch4
4
Jan 17 (Th)
Systems level power optimization
Rby-Ch5
5
Jan 22 (T)
continued
Rby-Ch5
6
Jan 24 (Th)
Interconnects
Rby-Ch6
7
Jan 29 (T)
Clock signaling
Rby-Ch6
8
Jan 31 (Th)
Low power memory
Rby-Ch7
9
Feb 5 (T)
Low power memory
Rby-Ch9
10
Feb 7 (Th)
Midterm exam
11
Feb 12 (T)
Low power CAS
Rby-Ch8
12
Feb 14 (Th)
Low power CAS
Rby-Ch10
13
Feb 19 (T)
Project proposal presentation
14
Feb 21 (Th)
Ultra low power/voltage design
15
Feb 26 (T)
continued
16
Feb 28 (Th)
Low power design flows
17
Mar 5 (T)
Continued
18
Mar 7 (Th)
Project presentation
19
Mar 12 (T)
Continued
20
Mar 14 (Th)
Course review
Rby-Ch11
Rby-Ch12
Note
Course Grade Policy
• Midterm examination
• Project proposal
• Final project report
– Presentation
25%
– Report document 25%
25%
25%
50%
Guidelines for Course Projects
• Each team is consisted of 2 members
• Two members are expected to contribute equally.
• Project options
– Selection of a major milestone paper published in a journal or a conference that
addresses low power design of VLSI circuits.
– Comprehensive and critical review of the paper.
– If possible, propose ways to improve the technical contents.
– Both proposals and final presentations will be peer reviewed by other teams.
From Transistor
toofIntegrated
Circuit
The Origin
VLSI Systems
From •Transistor
Invention device
to ICconcept (1945)
Shockley’s semiconductor
• Bardeen and Brattain’s point-junction transistor (1947)
• Shockley’s junction (sandwich) transistor (1950)
• Kahng and Attala’s MOSFET (1960)
1956 Nobel Prize, Physics
(J. Bardeen, W. Shockley,
and W. Brattain)
2000 Nobel Prize, Physics
(Jack Kilby)
Dec. 16, 1947
Germanium,1T, 1C, 3R, Oscillator,
0.04 inch X 0.06 inch (Sept. 12, 1958)
Intel 4004 (‘71), Pentium 3B (‘99), Xeon Nahalem (‘10)
Powered by Moore’s Law
9.5M transistors (2.5um), > 4,000X
(2X every 2.3 yrs)
2,300 transistors (10um)


2.3B transistors in 8-core Xeon Nehalem-EX (45nm)
240X over 3B processor (2X every 1.4 yrs)
.
Beyond Moore’s Law
.
.
Next Generation Flexible Electronic System
.
Ref. A. Nathan, et al., Flexible Electronics, Proc. of the IEEE, May 2012
k is typically
2
ΔΔΔ
𝑃𝑑𝑦𝑛𝑎𝑚𝑖𝑐 = α 𝐶 𝑉𝑑𝑑 ΔV f
𝑃𝑑𝑦𝑛𝑎𝑚𝑖𝑐 = α 𝐶 𝑉𝑑𝑑 ΔV f
• α denotes a fractional switching rate less than or equal to 1
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C is the switched capacitance
𝑉𝑑𝑑 is the power supply voltage
ΔV is the voltage swing
f is the clock frequency
To reduce 𝑃𝑑𝑦𝑛𝑎𝑚𝑖𝑐 it is desirable to reduce all these quantities so long
The performance goals can be met.
Hierarchy of Limits of Power
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5 -System
4 -Circuit
3 -Device
2 -Material
1 -Fundamental
Fundamental Limit
Ref. J. D. Meindl,Chapter 2, Low Power Digital CMOS Design, A. P. Chandrasakan & R. W. Brodersen
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The minimum allowable power supply voltage [R. Swanson72]
𝑉𝑠 𝑚𝑖𝑛 ≥ (2 − 4)
•
𝑘𝑇
,
𝑞
where
𝑘𝑇
=25mV
𝑞
at T=300°K, thus 50 to 100mV.
3 important limits are due to the basic principles of thermodynamics,
quantum mechanics, and electromagnetics.
•
R
𝑒𝑛
Mean circuit
Noise voltage
𝑅
Due to thermodynamicsGiven a noise voltage 𝑒𝑛 and a resistance R between a
node on a chip and the ground, the power max.
deliverable is
2
𝑒𝑛 2
,
4𝑅
𝑃𝑎𝑣𝑎𝑖𝑙𝑎𝑏𝑙𝑒 =(𝑒𝑛 /(R+R)) x R=
where 𝑒𝑛 2 = 4kTRB and thus
1
𝑃𝑎𝑣𝑎𝑖𝑙𝑎𝑏𝑙𝑒 = kTB, where B=bandwidth=
Δ𝑡
𝑃𝑠𝑖𝑔𝑛𝑎𝑙 ≥ γ 𝑃𝑎𝑣𝑎𝑖𝑙𝑎𝑏𝑙𝑒 and𝐸𝑠𝑖𝑔𝑛𝑎𝑙 = 𝑃𝑠𝑖𝑔𝑛𝑎𝑙 Δt ≥ γ kT
For T=300°K, γ =4, 𝐸𝑠𝑖𝑔𝑛𝑎𝑙 ≥ 1.66 𝑋10−20 joules=0.104 eV,
A limit to move an electron across a potential difference
of 0.104V.
P= γkT/𝑡𝑑 vs. P=h/𝑡𝑑 2
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Quantum-mechanical limit
A measurable energy change associated with switching must satisfy
the following limit based on the Heisenberg’s uncertainty principle:
ΔE ≥ h/𝑡𝑑 and P ≥ h/𝑡𝑑 2 where h= Planck’s constant=6.582x10−16
eV.s
P
10−3
P=h/𝑡𝑑 2
10−6
P= γkT/𝑡𝑑
10−9
10−6
𝑡𝑑
Hierarchy of Limits of Power
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5 -System
4 -Circuit
3 -Device
2 -Material
1 -Fundamental
System Level Approach to Minimizing Power
Level
Particular tasks
System
Power down, System partitioning
Algorithm
Complexity, Locality, Concurrency, Regularity,
Data representation
Architecture
Concurrency, Instruction set selection, Signal
correlation, Data representation
Circuit/Logic
Logic optimization, Novel circuits, Transistor sizing,
Voltage islands
Physical Design
Compact layout, Interconnects
Technology
SOI, Advanced packaging
Cray Supercomputer, Interconnects
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Complexity of interconnects (Rent’s rule)
Neuromorphic Computing
Cat scale cortical simulation on LLNL Dawn Blue Gene/P
supercomputer with 147,456 CPUs, 144TB main memory
(Communications of ACM, July 2011)
Ref. G. Snider, Memristor and Memristive Systems Symp., Nov. 2008
Cognitive Computing
With Neuroscience, Supercomputing, and Nanotechnology
Cognitive Computing may lead to
 novel learning systems
 Non Von Neumann architectures
 new programming paradigms
 integration, analysis and action on
vast amounts of data from many
sources at once
[Ref. D. Modha, et al., Communications
of ACM, Aug. 2011]
Mouse
Rat
Cat
Neurons (B)
0.016
0.055
0.763
2
20
Synapses (T)
0.128
0.442
6.10
16
200
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Monkey
Human
The Missing Link in Constitutive Relations
• V = R I (Resistor) V
• Q = C V (Capacitor)
• Φ = L I (Inductor)
V = d/dt Φ
Φ
• Φ = f (Q)
Q
dΦ /dt= df(Q)/dt
= df(Q)/dQ. dQ/dt
I = d/dt Q
V= M I
Memristance M=M(Q)
I
Nonvolatile Memristive Memory
• Nanotechnology enables ultra dense
Early 1kB memory based on p-Si/a-Si/Ag by Univ. Michigan
memory
 HP-Hynix collaboration on next generation memory products
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High quality memristive memory chips in a few years
Expected features (compared to FLASH)
Speed: >10x. Power <0.1X, Density >5X
S.H. Cho, et. al., Nano Letters, 2009;
New York Times, Aug. 2010
Nanostore-Based Distributed System
with 3D-Stacked Memristors
HP- Collocate processors and Memristor memory on chip
Axes of Device Requirements
(Memristor)