Transcript library

Design Automation
Design Automation II
High-Level Synthesis and
Optimization of VLSI Circuits
서강대학교 컴퓨터공학과
담당교수 : 김주호
1 -1
Design Automation
Topics
• Hardware modeling in hardware description languages such as VHDL and
Verilog
• Compilation techniques for hardware models
• Architecture-level synthesis and optimization including scheduling, resource
sharing, binding, and data path synthesis
• Logic-level synthesis and optimization techniques for combinational and
synchronous sequential circuits
• Library binding algorithms to achieve implementations with specific cell
libraries
Introduction
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Design Automation
• Circuit Technology
– First Generation: Vacuum Tube
– Second Generation: Transistor
• invented in 1947
• smaller, faster, cheaper
• IBM-709TX in 1958
– Third Generation: IC (Integrated Circuit)
• many tiny transistors on a single chip
• IBM-360 in 1964
– Fourth Generation: LSI (Large Scale Integrated), VLSI (Very ~)
• millions of transistors on a single chip
• DEC’s minicomputer, PDP-11 and IBM-370 mainframe in 1970, 1971
• Today’s personal computers
Introduction
1 -3
Design Automation
• ASIC (Application Specific Integrated Circuit) and CAD
– integrated circuit (IC) components performing a specialized task or a limited set of
tasks
– large market sharing
– issues
• volume of sales
• fast design time
• low design cost
• design quality measured by performance and manufacturing yield
– Computer-Aided Design (CAD) techniques
• reduction of design time
• optimization of design quality : optimization of large-scale circuits (millions of
transistors) is a complex problem
Introduction
1 -4
Design Automation
• Circuit Classifications
– semiconductor materials :
• Silicon on sapphire, or p-well and n-well
• Gallium-arsenide
– electronic device types :
• Complementary Metal Oxide Semiconductor (CMOS) : PMOS and NMOS
• Bipolar
• Combinaion of CMOS and Bipolar : BiCMOS
– analog and digital
• Analog circuit : information is related to the value of a continuous electrical
parameter such as voltage or current (power amplifier for an audio system)
• Digital circuit : information is related to the range of voltages at circuit internal
nodes having binary values (logic 0 and 1)
Introduction
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Design Automation
– Digital circuits in mode of operation : synchronous and asynchronous circuits
• Synchronous circuit : a global clock controls the timing of the circuit,
dominating digital circuit design, needs clock distribution
M
Combinational

M

• Asynchronous circuit : No global clock signal
input
Introduction
Combinational
1 -6
output
Design Automation
• Microelectronic Design Styles
– custom design: functional and physical design are hand-crafted, requiring an
extensive effort of a design team to optimize each detailed feature of the circuit
• expensive
• large design time
• high density, performance design
– semi-custom design:
semi-custom
cell-based
array-based
Standard cells
Macro Cells
Prediffused
Prewired
Hierarchical cells
Generators:
Gate arrays
Anti-fuse based
Memory, PLA,
Sea of gates
Memory based
Sparse logic
Introduction
1 -7
Design Automation
– Standard-cell design
• fundamental cells are designed by cell generators and stored in the library
• updates are necessary as semiconductor technology progresses
• library binding or technology mapping from the library
– Hierarchical standard-cell design: larger cells are derived by combining smaller cell
Introduction
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Design Automation
– Macro-cell based design
• automatic synthesis of memory arrays
– RAM : read/write memory (random access)
– ROM : read-only memory
• programmable logic arrays (PLA) : a regular layout structure for implementing
sum of products.
input
lines
AND
array
Product terms
ex) f1 = a’ + bc, f2 = a’b
Introduction
a
OR
array
b
F1(x1, x2, …,xn)
F2(x1, x2, …,xn)
…………………
Fm(x1, x2, …, xn)
c
f1 f2
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Design Automation
– Prediffused (mask programmable) based design
• Gate arrays
– Prewired (field programmable gate arrays) based design
• Anto-fuse based
• memory based
Density
Performance
Flexibility
Design time
Manufacturing time
Cost(low volume)
Cost(high volume)
Custom
Very high
Very high
Very high
Very long
Medium
Very high
Low
Cell-based prediffused prewired
High
High
Low
High
High
Low
High
Medium
Low
Short
Short
Very short
Medium
Short
Very short
High
High
Low
Low
Low
High
Comparison of design styles
Introduction
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Design Automation
• Design of Microelectronic Circuits
– design
• modeling: representing ideas, modeling by Hardware Description Languages
• synthesis and optimization: detailed model of the circuit and performance
enhancement for speed, area, and power
• validation: simulation and verification
– fabrication:
• start with lightly doped silicon wafers 75~150 mm diameter & 1 mm thick
die is one chip ( 10 mm)
• 4 categories of processes:
Introduction
1. Pattern transfer (lithograph)
2. Selective removal of material (etching)
3. Addition of material layers
4. Addition & activation of impurities
1 -11
Design Automation
• Pattern transfer (lithograph)
Pattern
generation tape
CAD DB
mask
Mask maker
Pattern
transfer
system
Patterned
wafer
Final full layout
1. Optical lithography (high throughput)
UV light (X-ray)  0.8 resolution limit
mask contains full wafer image (i.e. multiple chip image)
2. Direct write electron beam lith (direct step on wafer)
mask contains only 1 copy of chip (5x or 10x), low throughput, high resolution
CAD DB
E-Beam System
Patterned wafer
Before the exposure of each layer, wafer is coated with light-sensitive material
called photoresist
Introduction
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Design Automation
• Selective removal (Etching)
1. Wet etching : chemical acid
2. Dry etching : plasma, RIE (reactive iron etch), ion milling, …
Mast portions of layer that we want to keep such that etch will not attack parts.
• Addition of layers : SiO2 (Oxide), Si3N4 (Nitride), polysilicon, aluminum
• Addition of impurities : diffusion area n-type and p-type
Wafer is placed into impurity rich environment and heated.
Mask off regions to selective dope wafer.
– Testing
– Packaging
• Slicing
• Packaging
Introduction
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Design Automation
– Example of etching
Silicon wafer
photoresist
SiO2 (1m)
Silicon wafer
UV light
glass mask
mask pattern
photoresist
SiO2 (1m)
Silicon wafer
Silicon wafer
Introduction
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Design Automation
• Important Factors in Hardware System Design
– Time to Market
– Circuit Density : Memory capacity quadrupled every three years
• Problems with deep sub-micron design
– Thin wire : large interconnect delay, crosstalk with neighboring wires,
interleaving with power and ground wires ….
– Clock distribution
– Heat dissipation
– Power
• Dynamic power
• Short-circuit power
• Leakage power
• Supply voltage reduction
Introduction
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Design Automation
– Reliability
– Testability
– CAD tool’s availability
– Technology’s availability
– Library’s availability
– IP design
– Cost
– Chip area
– Chip performance
– More …..
Introduction
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Design Automation
• Computer-Aided Synthesis and Optimization
– Circuit Models : 3-levels
• behavioral (architectural) level : function regardless of implementation
• structural (logic) level : a model as an interconnection of components
• physical (geometrical) level : physical objects (transistors) of a design
– Synthesis : 3-levels
• Architectural-level (High-level) synthesis : Generating a structural view of an
architectural-level model. Assigning operators (adder, multiplier, …),
interconnections, and timing of their execution
ex) forward Euler method : differential equation y” + 3xy’ + 3y = 0 in [0,a] with
step-size dx and initial values x(0) = x; y(0) = y; y’(0) = u
in HDL model
diffeq {
Introduction
read(x, y, u, dx, a);
repeat { x1 = x + dx
u1 = u - 3*x*u*dx - 3*y*dx;
y1 = y + u*dx;
c = x1 < a;
x = x1; u = u1; y = y1; }
until ( c );
write ( y ); }
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Design Automation
• Logic-level synthesis : Manipulating a structural view of a logic-level model.
Library binding or Technology mapping from either schematic diagram or state
diagram. Optimization plays major role in logic-level design
• Physical design (geometrical-level synthesis) : Generating layout of the chip.
Final target of circuit design.
placement
routing
compaction
extraction
verification
Introduction
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fabrication
Design Automation
• Hardware system design
– Top-down design with libraries
– Synthesis tools
– Layout design : layout editor
– Symbolic layout : layout comjpactor
– Gate-level design : technology mapping, P&R
– RT-level design : Logic synthesis tool
– Behavioral-level design : Architecture synthesis tool
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Design Automation
• Design Flow Example
Functional Specification
VHDL Coding
Behavioral Simulation
Architectural/Logic Synthesis
Gate-level Simulation
Back annotation
In-place optimization
Placement & Routing
Macro-cell, Standard Cell, Gate Array, FPGA, IP
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Design Automation
• System-On-Chip
1 -21
Design Automation
• Hardware-Software Co-Design
– Balancing
• Performance of customized HW units
• Programmability of low cost SW components
– Reduction of Design Time
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Design Automation
• Hardware-Software Co-Design Example
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Design Automation
•
Hardware-Software Co-Design Related Fields
– Digital system design
– Analog, mixed signal, A/D, D/A, RF, …
– Mechanical components
• sensors
– VLSI CAD
• synthesis (high-level, logic, layout), simulation, …
– Software engineering
• software specification, generation, …
– Distributed system design
• network of communicating processors
– Real-time system design
• timing constraint (hard real-time, soft real-time)
– OS, compiler, computer architecture, …
1 -24
Design Automation
• Optimization : 3 design constraints (Delay, Area, Power)
area
power
Power-delay tradeoff
Area-delay tradeoff
delay
– combinational logic optimization problems
• Minimize area under delay constraints
• Minimize delay under area constraints
• Minimize power under delay constraints
– architectural-level optimization problems
• Minimize area under latency constraints
• Minimize latency under area constraints
• Minimize power under latency constraints
Introduction
1 -25
delay
Design Automation
• High-level to Logic-level Design Flow
HDL MODELS
ARCHITECTURAL LEVEL
LOGIC LEVEL
SEQUENTIAL
COMBINATIONAL
SCHEDULING
BINDING
SYNTHESIS AND
OPTIMIZATION
SEQUENTIAL
SYNTHESIS &
OPTIMIZATION
COMBINATIONAL
SYNTHESIS &
OPTIMIZATION
LIBRARY
BINDING
Introduction
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