Transcript ENC [e rms] - Agenda INFN

Activities in Pavia/Bergamo
on SVT strip readout and on
Layer0 pixels
Luigi Gaioni, Alessia Manazza, Massimo
Manghisoni, Lodovico Ratti,Valerio Re,
Gianluca Traversi, Stefano Zucca
INFN Pavia, Universities of Bergamo and Pavia
SuperB Workshop
Frascati, April 4, 2011
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SuperB Workshop, Frascati, April 4, 2011
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R&D on SVT strips and pixels
• Readout chips are needed for SVT strips
(layer 0-5, from short strips to long strips):
we are in the process of defining the specs
for these chips
• R&D on advanced pixel sensors for Layer0
is in progress:
– INMAPS (CMOS 0.18 mm)
- Pixels based on 3D integration
- CMOS 65 nm
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Specifications of readout ICs for SVT strips
• New readout chips with triggered readout of hit strips
with analog information are to be designed
• Evaluation of existing chips (such as FSSR2) showed
that none of them is able to comply with SVT specs
(performance and/or functionalities)
• Specs are very different from inner to outer SVT
layers (signal peaking time, sensor capacitance,…) so
that two different chips are most probably needed
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Noise evaluation in SVT layers: analog channel model
CD=detector
capacitance+strays
RS=series resistance of
the detector
CF=feedback capacitance
Cin=input capacitance
tp=peaking time
T(stp)=shaper transfer
function
We assume that the main contributions come from thermal and 1/f noise
in the preamplifier input device and from thermal noise in the
distributed strip resistance
Noise in the detector leakage current and in the reset network not
considered
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Dead time for an ideal RC2-CR shaping
1.2
<MIP>
RC2-CR shaper output [A.U.]
1
0.8
0.6
<MIP>/4
0.4
0.2
~2.4 t
p
0
0
1
2
3
4
5
6
Time [peaking time multiples]
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ENC estimate
Layer
CD [pF]
tp [ns]
ENC from
RS
[e
rms]
ENC
[e rms]
Channel
width
[mm]
Hit
rate/strip
[kHz]
Efficienc
y
1/(1+N)
0
11.2
25
220
680
1450
2060
0.890
50
650
1190
3010
1
26.7
2
0.969
268
100
460
930
3770
0.940
31.2
50
830
1400
3300
179
0.979
3
45.8
50
1480
2130
4120
52.5
0.994
4
52.6
1000
340
820
11370
21.9
0.950
5
67.5
1000
500
1010
13500
18.7
0.957
RC2CR shaping, ID=500 mA (current in the PA input device),
L=200 nm, N-channel input device, analog dead time=2.4 tp
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ENC estimate
Layer
CD [pF]
2
31.2
3
45.8
tp [ns]
ENC from
RS
[e
rms]
ENC
[e rms]
Channel
width
[mm]
Hit
rate/strip
[kHz]
Efficienc
y
1/(1+N)
50
830
1400
3300
100
590
1080
4140
200
420
860
5110
0.921
50
1480
2130
4120
0.994
100
1050
1600
5180
0.988
200
740
1240
6510
400
520
980
8050
0.979
179
52.5
0.959
0.975
0.952
RC2CR shaping, ID=500 mA, L=200 nm, N-channel input device,
analog dead time=2.4 tp
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ENC estimate
Layer
CD [pF]
4
52.6
5
67.5
tp [ns]
ENC from
RS
[e
rms]
ENC
[e rms]
Channel
width
[mm]
Hit
rate/strip
[kHz]
Efficienc
y
1/(1+N)
1000
340
820
11370
800
380
870
10730
500
490
1000
9430
0.974
1000
500
1010
13500
0.957
800
560
1080
12680
500
710
1250
11060
0.950
21.9
18.7
0.960
0.965
0.978
RC2CR shaping, ID=500 mA, L=200 nm, N-channel input device,
analog dead time=2.4 tp
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Comments
• From the noise standpoint, it would be obviously
desirable to reduce the strip resistance as well as the
detector capacitance (by increasing the strip readout
pitch: what about the strip hit rate?)
• According to these estimates, detection efficiency in a
layer 0 with striplets is < 90% at full luminosity (with
safety factor)
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Monolithic Active Pixel Sensors in the
INMAPS process (CMOS 180 nm)
The deep P-well can be used to prevent parasitic charge collection by nwells competing with the sensing electrode
The technology provides epitaxial layers 5 or 12 mm thick with a
maximum resistivity of 50 Ω*cm
High resistivity epitaxial layers (1 kΩ*cm) 12 or 18 mm thick are also available.
Deep P-well combined with high resistivity epi-layer increases the charge
collection efficiency. This makes it possible to use a simple nwell diode
instead of a large DNW sensor, reducing the overall noise.
INMAPS CHANNEL READOUT CHAIN
Vbl=750 mV
Imir=20 nA
Cfb=5 fF
C1=160 fF
C2=25 fF
A preliminary design and layout of each block in the figure above
has been carried out.
All the simulations have been performed keeping CD=40 fF.
Use of a mirror feedback configuration for C2 discharge instead of
the transconductor in order to reduce the overall noise and
threshold dispersion.
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INMAPS: SIMULATED PERFORMANCE AND PLANS
P=18 uW per pixel
Output waveform tp=230 ns
ENC=30 e (CD=40 fF)
Threshold dispersion=13e (at the shaper output)
Threshold dispersion=23e (including discriminator contribution)
15um
Charge sensitivity = 970 mV/fC
In the INMAPS technology, we plan to test a fast readout
architecture (“hybrid-pixel-like”, as in APSEL MAPS) with pixellevel sparsification and time stamping, which seems to fit at best
the high background rate of Layer0.
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3D integrated MAPS from the first 3D-IC
MPW run: still waiting for 3D chips
• In 2009, the Italian VIPIX
collaboration submitted 3D active
pixel devices in the first run of the
3DIC Consortium hosted by Fermilab.
• In this run, we designed 3D MAPS
with two layers (“tiers”) of the 130 nm
CMOS process by Chartered
Semiconductor, vertically integrated
with the Tezzaron interconnection
technology.
• In January 2011, we received the first
samples, before the interconnection
(see talk by S. Bettarini). The 3D
interconnection process by Tezzaron
is scheduled this week.
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The second 3D-IC run:
VIPIX plans and designs
• The VIPIX collaboration is at an advanced stage in the design work
for a second MPW run in the 3D Tezzaron/Chartered process.
• This second run will take place about 3 months after we get 3D
devices from the first run, to allow enough time for testing
• No change in 3D integration technology is foreseen for the second
run (TSV drilled at Chartered)
The following devices will be included by VIPIX in the second run,
targeting SuperB SVT specifications:
• “test beam grade” MAPS : 100x128, 50 um pitch (~32 mm2
active area) with high rate sparsified readout architecture
• a 3D readout chip for high resistivity pixel sensors (similar
architecture) : 128x32, 50 um pitch (~10.3 mm2 active area)
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The analog section of the 3D readout
chip for high resistivity pixels
Main front-end design features
Block diagram of the analog front-end circuit
for high resistivity pixel sensor
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CD [fF]
(detector+bonding)
150
CF [fF]
32
C1 [fF]
25
C2 [fF]
12
Preamplifier Input Device
[mm/mm]
18/0.25
Analog Supply [V]
(AVDD)
1.5
Analog Power Dissipation
[mW/pixel]
10
Peaking Time [ns]
(Qinject =16000 e-)
260
Charge sensitivity
[mV/fC]
48
ENC
[e- rms]
130
Threshold dispersion
[e- rms]
560 (before
corr.)
65 (after corr.)
16
Analog front-end for the ApselVI 3D MAPS chip
(v2)
C
Design features and simulation
results
2
W/L=32/0.25, ID,PA=16 mA
Total power dissipation=33 μW
CD=300 fF
320 ns peaking time
Charge sensitivity: 850 mV/fC
A(s)
C1
VTHR
CF
ENC: 34 electrons
Threshold dispersion: 103 electrons
VREF
900
500
Shaper peak amplitude [mV]
850
Shaper Output [mV]
800
750
700
800 e1000 e-
650
1200 e1400 e-
600
400
300
200
100
INL = 2.1%
1600 e550
0
0
1
2
3
4
5
0
Time [ms]
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500
1000
1500
2000
Input charge [electrons]
2500
3000
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Voltage drop on analog power/ground lines: compensation
May be an issue with large matrices of relatively current-hungry
detectors (e.g. DNW MAPS): front-end features can degrade due to
voltage drop on the power and ground lines causing changes in some pixel
current sources – shaper input branch and transconductor
This problem can be overcome if currents are correctly mirrored in
pixel cells
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SuperB SVT and the AIDA project
• February 1st, 2011 was the kick-off date for the AIDA project, a
EU-funded FP7 program addressing infrastructures for detector
development for future particle physics experiments
(www.cern.ch/aida).
• In AIDA, WorkPackage3 aims to establish a network of groups from
European universities and high energy physics research institutes
working collaboratively on 3D integration technology for thin pixel
sensors with complex pixel-level functionality, with small pixel size
and without dead regions (as needed by SVT Layer0).
• A major goal of AIDA WP3 is to build a demonstrator based on 3D
integration. WP3 plans to follow a “via last ” approach to 3D integration
to build a 2-layer device in heterogeneous technologies (e.g., highresistivity pixel sensors and CMOS readout chips).
• We are organizing a 1-day workshop in Bergamo, Italy, on May 23rd,
2011. The goal of this workshop is to begin a discussion with industries
and research institutes which may provide 3D technology to the AIDA
WP3 network
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AIDA WP3 and SVT Layer0
AIDA WP3 will pursue an alternative approach to 3D integration with
respect to the 3D-IC consortium. This opens up new opportunities and
technical solutions for a Layer0 based on 3D integrated pixels.
3D-IC consortium:
3D integrated circuits with the Tezzaron process
“via first” process, where TSVs are drilled at the foundry in the early
stages of CMOS wafers processing. Very high density interconnections
(< 10 mm) are possible.
AIDA WP3:
Advanced pixel sensors based on 3D integration of 2 layers in
heterogeneous technologies
“via last” process, 4-side buttable device with low density
interconnections in the device periphery.
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65 nm CMOS MAPS
• The demand for higher in-pixel functionalities along with the
reduction of pixel cell size drives the interest of the designers
community towards sub-100 nm CMOS processes in the design of
mixed signal front-end electronics
• We fabricated a prototype chip with active pixel sensors (same
architecture as APSEL chips) and fast front-end circuits in the
Low Power 65 nm CMOS process by IBM (10LPE/10RFE)
• Tests have just started, preliminary results are available
10
50
0
0
Shaper Output [mV]
Shaper Output [mV]
-10
Fast
front-end
-20
-30
-40
Qin=8000 eQin=12000 eQin=16000 eQin=20000 e-
CD = 50 fF
Vfbk,pa = 220 mV
Vfbk,sh = 870 mV
tp = 42 ns
ENC = 212 e-rms
-50
MAPS
analog
channel
-50
-100
-60
Qin=600 eQin=800 eQin=1200 eQin=1000 e-
CD = 350 fF
Vfbk,pa = 220 mV
Vfbk,sh = 915 mV
tp = 630 ns
ENC = 58 e-rms
-150
-200
0
0.2
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0.4
0.6
Time [ms]
0.8
1
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2
4
6
Time [ms]
8
10
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Conclusions
• R&D on advanced pixels is in progress, various
technologies are being explored
• Concerning SVT strips, real work on chip design
has to start soon (two different chips are
needed)
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Backup slides
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Via First Approach
• Through silicon Via formation is done either before or
after CMOS devices (Front End of Line) processing
Form vias before transistors
IBM, NEC,
Elpida, OKI,
Tohoku, DALSA….
Tezzaron, Ziptronix
Chartered, TSMC,
RPI, IMEC……..
Form transistors before vias
TWEPP-08
24
Via Last Approach
• Via last approach occurs after wafer fabrication and
either before or after wafer bonding
Zycube, IZM,
Infineon, ASET…
Samsung, IBM,
MIT LL, RTI,
RPI….
Notes: Vias take space away from all metal layers. The assembly process
is streamlined if you don’t use a carrier wafer.
TWEPP-08
25
Bonding Choices
Fermilab
experience
Electrical and Mechanical Bonds
1) Bonding between Die/Wafers
a) Adhesive bond
Polymer
(BCB)
b) Oxide bond (SiO2 to SiO2)
c) CuSn Eutectic
Sn
Cu
d) Cu thermocompression
SiO2
bond
Cu3Sn
(eutectic bond)
Cu
bond
Cu
e) DBI (Direct Bond Interconnect)
Metal
(MIT LL)
(RTI)
(Tezzaron)
Oxide
bond (Ziptronix)
Metal bond
For (a) and (b), electrical connections between layers are
formed after bonding. For (c), (d), and (e), the electrical
and mechanical bonds are formed at the same time.
TWEPP-08
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TEMPERATURE VARIATION
The channel readout has been simulated in the temperature range
between 0°C and 80°C.
Gain temperature coefficient = -420 uV/(°C fC)
Charge sensitivity = 970 mV/fC
Taking into account a temperature variation of 10°C for each 10 cm
module, considering a 1 cm chip width, we have a variation of 1°C per
chip, that corresponds to:
Charge sensitivity variation= [-0.42 mV/(°C fC)] / [970 mV/fC] =
= -0.04%
Analogous considerations can be done regarding the baseline variation
depending on the temperature:
Baseline temperature coefficient = 0.56 mV/°C
VoutSHAPER=121 mV @ Qinj=800 electrons
Considering a 1°C/chip variation:
σ2VblΔT=[0.56 mV/121 mV]*800e=4 electrons due to a 1°C variation
σ2Vbl=23 electrons due to mismatch variations (Discriminator output)
[σ2VblΔT/σ2Vbl]2=3%
Vertically integrated MAPS in the second
3D-IC run: APSEL
Beam axis
1.6 mm 0.5 mm
0.25 mm
5 mm
~ 38 Pad – pitch 130 mm
128x100 pixel matrix
50 mm pitch
Active area=32mm2
Submatrix 2: 128x50
Piste data line di 2 sottomatrici
0.16 mm
~ 38 Pad – pitch 130 mm
Submatrix 1: 128x50
~ 38 Pad – pitch 130 mm
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6.4 mm
Readout=8mm2
0.120 mm cut
line
0.16 mm
Area~x2x area from FE32x128
5.56 mm
Piste data line di 2 sottomatrici
8.99 mm
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•
•
•
An example of how 3D integration is exploited in the
second run: in-pixel logic with time-stamp latch for a
time-ordered readout
No Macropixel
Timestamp (TS) is broadcast
to pixels & pixel latches the
current TS when is fired.
Matrix readout is timestamp
ordered
•
•
•
A readout TS enters the pixel,
and a HIT-OR-OUT is generated
for columns with hits associated
to that TS.
A column is read only if HITOR-OUT=1
DATA-OUT (1 bit) is generated
for pixels in the active column
with hits associated to that TS
T
S
Co
m
p.
DATA-OUT
• This more complex in pixel logic will be
HIT-OR-OUT
implemented with 3D integration without
reducing the pixel collection efficiency even VHDL simulation of the data push
chip (100MHz/cm2 input hit rate)
improving the readout performance
(readout could be data push or triggered) • Readout Effi > 99 % @ 50 MHz
clock with timestamp of 200 ns.
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In this prototype
the digital
section is kept to
a minimum (latch,
OR gate, tristate buffer). It
is planned to
include
sparsification
and timestamping logic at
the pixel level in
more advanced
versions (room
for this already
available)
Cell layout
40
um
n-well PMOSFETs
(area ≈ 50 µm2)
Sensor
(area ≈ 360 µm2)
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APSEL65 DNW MAPS
Classical signal processing
chain for capacitive detector
The analog processor
includes a charge
sensitive amplifier, a
shaping stage and a
threshold discriminator
 binary readout
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