Transcript ASIC Design

VHDL & ASIC Design
ITSoC Lab.
Prof. Young-Chul Kim
1
Course schedule

VHDL & Digital System Design

Term project #1: Digital watch

Midterm: Presentation & demo project #1

ISP & FPGA Implementation

Term project #2: ISP Algorithm & design

Final: Presentation & demo project #2
2
Contents

Agenda

ASIC Design

VHDL and Background

VHDL and ASIC Design Environment

Modeling, Synthesis & FPGA Implementation

VHDL Evolution and Future
3
Agenda
I.
Mobile Society Change
1.
2.
II.
PC -> Mobile Communication
Component -> System
Design Methodology
1.
2.
ASIC Design Flow
SoC Design Flow
4
Shift 1: From PC to Communications Centric
Services
Broadband
Network
100Mb/sWLAN
RF
20Gop/s
WWW
Java
Configurable
Multi-Standard
Info Plug...
<1 Watt
LAN
MPEG 4-7
100 Gop/s
??
5 Gtr/s
10 Watt
5
-> Domain Specific Computing
Shift 2: Chip from Component -> System
Services
Network
embedded C
RF
asp
opamp
System on
Filters AD/DA
dspP
IC
ASIP
memory
IP
µP
µC
gate
RT-ops
FSM
ASIC
FPGA
Silicon Board
VHDL
OO
cC++
Softwar
eHardware
1960
Design Software
70
80
90
2000
2010
t
6
Environmental Changes in Mobile Society

PC Era


Internet Era


Beginning of PC Communication, E-mail (WS, PC), WWW
Mobile Phone Era



Beginning of 8-bit/64K Memory PC era from late in
1970’s
Beginning of Analog Mobile Phone, Digital Phone era
from mid of 1980’s
3rd Generation of IMT-2000 – Any where, any time, any
service
Post PC Era

Beginning of various types of smart IT industry and
network information appliances
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Post-PC Silicon System in 2010
40nm , 1G+ Transistors
www
gps
Speech
Pen
Vision
Bio
Motion
Security
Sensors
RF / Analog
100 MByte
32 Bit ASPP’s Distributed
Memory
Embedded
Software
>1GHz
<1 Watt
<1 Volt
Re-configurable Interconnect
10 M gate
10 M Gate
Re-configurable Hardwired
Computing
Logic
Display
Sound
Data
Bio
Actuators
50 GIPS-500GOPS
ENERGY/OP : 100
FLEXIBILITY - REUSE - IP
More than IP assembly!!
8
Key Enabling Technologies
RF-CMOS
BiCMOS
System
partitioning
Keys to 3G
and beyond
Firmware
Memories
processing power
power consumption
Cores
memory capacity
Conversion Technology
PA-Technology
System Architecture
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Productivity Gap in Hardware Design
Source: sematech97
A growing gap between design complexity and design productivity
10
100,000
Logic transistors per chip ( millions )
10,000
G
F
58% CAGR
E
C, D
21% CAGR
A, B
0.001
1981
1995
Productivity
(thousands of transistors per staff month)
Increasing Designer Productivity
0.01
2009
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1. ASIC Design –The Silicon Evolution
Log scale
1 G
256 M
64M
16M
100 M
IBM gate
array
Pentium
P7
4M
10 M
R0
1M
1 M
256M
64K
100 K
80386
80286
16K
4K
Memory(DRAM)
Microprocessor/
Logic
DSP
TMS320C15
8086
1K
LSI Logic
gate array
TMS320C40
TMS320C30
68000
10 K
Mitsubish
gate array
TMC320C80
8080
1 K
4044
70
74
78
82
86
90
94
98
10x every 6 years
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ASIC Design - Technology Diffusion
Technology Diffusion is Accelerating
PCS
PCs
Cellular
VCRs
Color
TV
Cable
TV
Black &
White TV
1 Million
0.5
1
5
10
15
Years to 1 Million Sales
Mobile and Wireless Communications - Richard Siber (617) 982-9500
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ASIC Design - Profit Loss
40
33
22
30
20
10
4
0
+50% develp. Cost
+9% Product Cost
+6 month develp.Time
Source: McKinsey
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ASIC Design-VLSI Crisis


feature size - decreases by a factor of 2 in every 4 years.
chip size - increases
–



total transistor count rises by a factor of 2 in every 18
months.
fabrication cost - doubles for each generation
programmer productivity
–

5 mm 1977, 15-20 mm in 2000, 25-30 mm in 2010
30 lines/day ($20/line) ~ 0.5 lines/day
designer productivity
–
–
30 transistors/day
30 HDL lines/day, 300 gates/day, 1200 transistors/day
15
ASIC Design-VLSI Crisis

HDL based design
–
–
–

Formal verification


simulation
logic synthesis
behavioral synthesis
Equivalence verification of HDL based designs of different
abstract levels.
Intellectual Property


vendor library
synthesizable core
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ASIC Design-Design Reuse

More than 100M gates in 40 nm





10 – 1M gates per synthesis module
20 - 100 synthesis modules per chip
behavioral synthesis
100M gates by the years 2010
Design Reuse



constant project team sizes
shrinking project completion times
Large portions of the chip will result from reusing existing
blocks.
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ASIC Design-System Design

Building blocks




image/video processing
speech codec
communications
ASIC Design




becomes a system integration
system level analysis of available building blocks
Balancing of available IP building blocks
product differentiation at the system level
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ASIC Design
-Intellectual Property

IP Development / Integration House



ASIC Design




Diverse market needs
e.g.> graphics chips with digital modem capability
becomes a system integration
performance analysis of availiable building blocks
balancing of available building blocks
Reusing IP Building Blocks


only viable approach to designing over 1M gates reasonable
time.
Reusing IP building blocks developed outside is the way to
merge knowledge from different applications onto a single chip
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ASIC Design
-Intellectual Property

On Silicon IP(hard IP)




Off Sillicon IP(soft IP)




ASICs
chip sets
programmable DSPs
synthesizable core
a reference implementation in sillicon
adds a credibility
Firm IP(soft IP)

RTL level libraries
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ASIC Design
-Levels of Abstraction

Architectual /Algorithmic



RTL



flow of data and control signals whthin / between functional
blocks.
schedules assignments at clock edges.
Gate


described in terms of the algorithms the system performs.
High lebel design tradeoffs, e.g. hardware /software codesign.
interconnection of switching elements (gates).
Switch


describes logic behavior of transistor circuits.
Evaluates conflicts caused by signal strengths of multiple nets.
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Market Pressures

Size of Custommer Telecom Market: < US$ 2T

Products:




Signal-Dominated HW Systems Under SW Control
Protable, Low-Power, Manufacturable, Time to Market
Average Lifetime of a Consumer Product: 6-18
mos.
Success Depends Critically on the Ability to
Design these Systems FAST!
22
When Does One Use Behavioral
Synthesis

Use behavioral synthesis when





Algorithmic descripion exists
Complex data flow and/or memory access
Operations can be moved
Designs specification still changing
Need to explore architecture, pipelining, etc.
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Behavioral Synthesis
CYC# OP
SCHEDULING
HARDWARE
ALLOCATION
1
2
3
4

Looks at high-level constraints
–

Latency, Throughput, Clockperiod goals
Extracts control /data flow behavior (Scheduling)
–
–
Assigns operations to resources and states
Assigns variables to storage elements (Allocation)
–
–
–
optimization of storage
decides if temporary storage necessary
FSM generated automatically
–
–
defines state /state transitions
cycle /cycle implementation of behavior
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Behavioral Synthesis: Definition
input
FOR I in 0 TO 2 LOOP
m
WAIT until clk’event and clk = ‘1’;
o
IF (rgb[i] < 248) THEN
m
p = rgb[i] mod 8;
R
input
q = filter(x,y)*8;
output
END IF;
…...
clk
Enable
Instructions
Scheduling
Functional units
Operations
Allocation
Registers
Variables
Loop pipelining
Memories
Arrays
Chaining
Multiplexers
signals
Multi cycle operations
DW components
constraints
Memory management
Reset style
Clocking sytyle
Collection of techniques for sequential optimization
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Design Automation
▶
Evolution in Computer Technology
- Performance, Storage Capacity,
▶
GUI Technology
Evolution in Integrated Circuits and Design
- Advanced Design technology and tools
▶
Help Designer’s works and decision as an assistant
26
HDL Design & Computer Programming
비교
하드웨어설계
단 계
동작적 기술
(HDL 설계)
컴퓨터프로그래밍
고급언어 프로그램
3단계
합성
2단계
구조적 기술
(게이트 레벨 설계)
실리콘 컴파
일러
어셈블리어 프로
그램?
고급언어 컴
파일러
어셈블러
1단계
레이아웃 설계
기계어 프로그램
27
What is Synthesis ?
▶ One of the most important process in designs
using HDL
▶ Synthesis = Translation + Optimization
(translation)
(optimization)
▶ Translation : Behavioral or RTL description
Structural or gate-level description
▶ Optimization : in design area and delay
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2. VHDL, History and Background






ASIC Technology
Logic synthesis
VHDL
Why VHDL synthesis is necessary ?
Adv. & Disadv. of VHDL
Reality of VHDL synthesis
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ASIC Technology(1)
Advance in
IC fabrication
technology
Advance in
Computer &
Design tools
ASIC
(Application Specific IC)
Appearance
semi-custom )
-Low Volume Production( application specific )
-Shorter design turnaround time
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ASIC Technology(2)
Minimize mask pattern
in fabrication process
full-custom
IC
- Increase in gate density
- Enhancement in speed(performance)
- Decrease in cost
semi-custom
IC
- Gate Array
- Standard Cell
- PLA, PAL
ASIC
ASIP
(co-design)
- FPGA(Field Programmable GA)
- PLD(Programmable Logic Device)
31
Logic Synthesis
schematic based
design process
language based
design process
circuit design
with schematic editor
circuit design
with HDL(Hardware
Description Language)
simulation
logic
synthesis
simulation
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VHDL(Very High Speed IC HDL)
- HDL workshop in 1981
Rise of necessity of new HDL development
- USA, Publication of Documents for
Department of Defense Requirements for HDL
- Birth of VHDL version 7.2 (USA DoD) in 1984
- Birth of IEEE Standard 1076-1987 VHDL in 1987
- VHDL 1076-1993 VHDL established in 1993
(reflect additional requirements for synthesis)
33
Why VHDL synthesis is necessary ?
circuit design
with HDL
logic
synthesis
Circuits
complexity
Performance
Evaluation
Early design
Error detection
HDL independent on
Circuit complexity
Easy and Early
Design change
Automatic netlist extraction
Decrease DAT
simulation
34
Advantage of VHDL Synthesis
 Reduced design cycle – Reduced design error
 Design quality enhancement
- Search in ease different design types and methodology
 Independence of vendor and fabrication technology
 Reduced design cost - design re-usability
 Easy design management
- Introduction of structured design concept using HDL
 Agreement with USA standard(IFIP 172)
35
Disadvantage of VHDL Synthesis
 Cultural change in design
- Design process based on language
- Main goal: Digital system design
 Detection and modification of design errors
- Difficult to understang logic synthesis results and
synthesized circuit layout
- Difficult to analyse propagation delay
36
Reality of VHDL Synthesis
 Once modeling in VHDL, synthesis tools make results
completely expected or intended (?)
E.g. A = B x C
 VHDL is not a programming language -> design lang.
 H/W design experience is very important
 Results depend highly on synthesis tools
37
2. VHDL & ASIC Design Environment

Synthesizable funtions & Basic
synthesis principles

Design hierarchy

ASIC design process

Useful VHDL synthesis methodology
38
Synthesizable functions
 Combinational logic functions
- primitive logic gates, decoder, multiplexer
- adder, subtractor , comparator, multiplier etc.
 Sequential logic functions
 Counters and function using counters
- up/down counter, timing generator, event counter etc.
 Registers and latch functions
- register, latch, shift register, accumulator etc.
 Control logic circuits
- sequencer, controller, finite state machine etc.
39
Basic Synthesis Rules
 Not every VHDL code can be synthesized.
 Code directly in VHDL what you want to design
 Synthesized results may not satisfy timing delay constraint
required
40
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detailed design
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abstract design
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Layout ·¹º§
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41
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ASIC 설계 프로세스
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½Ã¹Ä·¹À̼Ç
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°áÁ¤
layout Á÷Àü ¹× Á÷ÈÄ
¼³°è °ËÁõ
prototype ASIC Á¦Á¶ ¹× Å×½ºÆ®
42
ASIC Design Process(1)
 System development plan and functional decomposition
- Analyse advs and disadvs of algorithms
- Decompose entire design into H/W and S/W
- functional definition of low level modules
 Decide block diagrams and design specification
- Decompose into detailed H/W function
- With which VHDL designs are coded
- Consider items for system evaluation such as gate count
43
Example: High-level block diagram
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¸Þ¸ð¸®
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RAM ¸Þ¸ð¸®
44
E.g. Block diagram of Sigal generator “A”
LoadPW
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µ¥ÀÌŸ ¹ö½º
ÆÞ½º Æø (Pulse Width)
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Gate Spacing
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16 MHz Ŭ·Ï
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8 ºñÆ®
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½ÅÈ£
Ä«¿îÅÍ
(8 ºñÆ®)
¸ðµÎ '1'ÀÎ ½ÅÈ£
°ÔÀÌÆ® Ãâ·Â
45
ASIC Design Process(2)
 Test and Simulation Plan
- Improve controllability and observability  Improve yield
- Ways to generate test inputs(e.g: 24-bit counter, 2 24 )
 Logic circuit design
- Common(共用) function identification  Design in Macro
- VHDL code and Simulation pattern generation for each
function and block
46
Logic design flow
ȸ·Î µµ¸é
ÀÔ·Â
Netlist »ý¼º
°ÔÀÌÆ® ·¹º§
³í¸® ½Ã¹Ä·¹À̼Ç
VHDL
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RT ·¹º§
VHDL ½Ã¹Ä·¹À̼Ç
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47
ASIC Design Process(3)
 Simulation
- compile and link VHDL source codes
- Simulation of partial/whole design
( E.g : half-adder and AND gate )
 debugging
 Logic Synthesis
- Select ASIC vendor (Use of corresponding component library)
- Performance optimization and logic minimization
 Verification
- Gate propagation delay time analysis of physical layout result
- I/O pin assignment, ERC ( Electrical Rule Checking )
48
Guideline in VHDL Synthesis
 Be well informed of logical structure of certain block
diagram before coding in VHDL .
 Test with same test pattern in order to make sure that
VHDL design and final gate-level design are same and
correct.
49
3. VHDL Modeling, Synthesis and FPGA
Implementation Example

VHDL modeling for syntheis

Simulation and logic synthesis
example of VHDL modeling

FPGA implementation

Example of performance
optimization and area minimization
50
VHDL Modeling for Synthesis
 Abstract behavioral-level modeling
(Behavioral Descriptions)
 Register transfer-level modeling
(Dataflow Descriptions modeling)
 Structural-level modeling
(Structural Descriptions)
51
Abstract behavioral-level modeling
(Behavioral Descriptions)
architecture behavioral of eqcomp4 is
begin
comp : process (a, b )
begin
if a = b then
equals <= ‘1’ ;
else
equals <= ‘0’ ;
end if ;
end process comp;
end behavioral ;
52
Register transfer-level modeling
(Data-flow Descriptions)
architecture dataflow of eqcomp4 is
begin
equals <= ‘1’ when (a = b) else ‘0’;
-- equals is active high
end dataflow ;
53
Structural-level modeling
(Structural Descriptions)
architecture structural of eqcomp4 is
signal x : std_logic_vector (0 to 3);
begin
u0 : xnor2 port map (a(0), b(0), x(0));
u1 : xnor2 port map (a(1), b(1), x(1));
u2 : xnor2 port map (a(2), b(2), x(2));
u3 : xnor2 port map (a(3), b(3), x(3));
u4 : and4 port map (x(0), x(1), x(2), x(3), equals);
end structural ;
54
VHDL Modeling Ex: Full Adder
 1-bit half-adder(HA) VHDL modeling
- Data-flow Descriptions
- Behavioral Descriptions
 1-bit full-adder(FA) VHDL modeling
- Structural Descriptions(2 HA + OR gate)
- Behavioral Descriptions
55
half adder (1): entity declaration
entity half_adder is port (
a, b :
in bit ;
sum, carry : out bit );
end half_adder ;
a
b
half adder
sum
carry
56
Example 1 : half adder(2)(architecture body)
(Register Transfer Level Modeling)
architecture RTL_description of half_adder is
begin
process begin
sum <= a xor b ;
carry <= a and b ;
wait on a, b ;
end process ;
end RTL_description ;
57
Example 2 : half adder(3) (architecture body)
(Behavioral Modeling)
architecture behav_description of half_adder is
begin
process begin
if (a = b) then sum <= '0' ;
else sum <= '1' ;
end if ;
if (a = '0') or (b = '0') then carry <= '0' ;
else carry <= '1' ;
end if ;
wait on a, b ;
end process ;
end behav_description ;
58
Ex. 1 & Ex. 2 VHDL synthesis results
(logic equation, critical path, device utilization)
Design Equations
carry = a * b
sum = a * /b + /a * b
Worst Case Path
tPD = 8.5 ns for the path (a  sum, a  carry )
Utilization (using Package CY7C371-143JC)
Total PIN signals
4/38
Macro-cells Used
2/32
Unique Product Terms 3/160
59
Simulation result (half adder)
propagation delay
60
full adder(1) : entity declaration
entity full_adder is port (
x, y, c_in : in bit ;
s_out, c_out : out bit ) ;
end full_adder ;
x
y
c_in
full adder
s_out
c_out
61
full adder(2): architecture body
architecture structure of full_adder is
signal temp_sum, temp_carry_1, temp_carry_2 : bit ;
component half_adder port (
a, b
: in bit ;
sum, carry : out bit ) ;
end component ;
component or2 port (
i1, i2 : in bit ;
o
: out bit ) ;
end component ;
begin
port map ( … ); ...
end structure ;
62
full adder(3): block diagram
x
s_out
y
Full_adder
c_out
c_in
x
y
c_in
U0:
half_adder
temp_sum
U1 :
half_adder
s_out
c_out
temp_carry_2
U2
temp_carry_1
63
full adder(4): structural descriptions
u0 : half_adder
port map ( a => x, b => y,
sum => temp_sum, carry => temp_carry_1);
u1 : half_adder
port map ( a => temp_sum, b => c_in,
sum => s_out, carry => temp_carry_2 );
u2 : or2
port map ( i1 => temp_carry_1, i2 => temp_carry_2, o => c_out );
x
y
a
b
U0
sum
carry
temp_sum
Temp_carry_1
64
full adder(5): logic synthesis result
65
full adder(6) : Behavioral Modeling
architecture behav_description of full_adder is
begin
process
variable I : integer ;
if (x = ‘1’) then I <= I + 1 ; end if;
if (y = ‘1’) then I <= I + 1 ; end if;
if (c_in = ‘1’) then I <= I + 1 ; end if;
if (I = ‘1’) or (I = ‘3’) then s_out <= ‘1’ ;
else s_out <= ‘0’; end if;
if (I > ‘1’) then c_out <= ‘1’ ;
else c_out <= ‘0’; end if;
wait on x, y, c_in ;
end process ;
end behav_description ;
66
full adder(7): logic synthesis result
67
FPGA implementaion of VHDL modeling
 Standard Cell
- warehouse store like structure
 Gate Arrays
- Prefabricated device except metal layer
 PLD(Programmable Logic Devices)
- 2-stage arrays : AND plane + OR plane
- PROM(Programmable ROM), PLA, PAL
 FPGA(Field Programmable Gate Arrays)
- Kind of Expanded PLD
68
FPGA
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ä³Î
¼öÆò ¹è¼±
ä³Î
logic cell
³í¸® ¼¿
69
Device
selection
VHDL
modeling
Synthesis
constraints
Synthesizer
Netlist or
Boolian equation
Placement & Routing program
Result file
Simulation after layout
(timing analyzer) (VHDL or other formats)
Test benches
Device programming
file
(JEDEC format)
VHDL simulator
Graphic wave form
Data file
70
Device Selection
71
VHDL (compilation)
72
CPLD Implementation example(1)
73
CPLD 구현 예(2) - reduced
74
Timing analysis result per path
75
Analysis result – resource utilization
76
Performance optimization & area minimization
cost = area
gate density 
performance = speed
Delay of critical path 
area minimization
performance
optimization
ASIC implementation with best performance and lowest cost
77
Example: delay enhancement
Sum <= BusA+BusB+BusC+BusD
A
B
C
D
+
Sum <= (BusA+BusB)+(BusC+BusD)
A
B
C
+
+
D
+
+
+
SUM
SUM
78
Example: resource sharing(1)
Y <= A + B When Sel = ‘1’ Else Y <= C + D
Which one to choose?
A
C
B
MPX
D
Sel
A
MPX
ADD
Y
B
C
ADD
Sel
D
ADD
MPX
Y
79
Example: resource sharing(2)
Y <= A + B When Sel = ‘1’ Else Y <= C + D
A. Two multiplexers and one adder
MPX1 <= A When Sel = ‘1’ Else C;
MPX2 <= B When Sel = ‘1’ Else D;
Y <= MPX1 + MPX2;
B. Two adders and one multiplexer
Sum1 <= A + B;
Sum2 <= C + D;
Y <= Sum1 When Sel = ‘1’ Else Sum2;
80
Example: Logic gate minimization(1)
Z<= (A nand B) or (not(C))
Z<= (A and B) nand C
A
A
B
B
Z
C
Z
C
Z<= (A nor B) and (not(C))
Z<= (A or B) nor C
A
A
B
B
Z
C
Z
C
81
Example: logic gate minimization(2)
C <= A or (B and not (Select));

Z <= A when Select = ‘0’ else C;
Z <= A;
82
Example: Delay optimization(1)
Delay minimization in critical path
SigA <= ‘1’ When Count = ‘1101000011001010’ Else ‘0’;
Z<=(((((A and B) and C) and D) and E) and F) or G
A
B
C
D
E
F
G
Z
83
Example: Delay minimization(2)
Separate with And/Or terms
Y<=(((((A and B) and C) and D) and E) and F)
Z<=Y or G
A
B
C
D
E
F
G
Y
Z
84
Example: Delay minimization(3)
Minimization of propagation delay from A to Z
Z<=(((((F and B) and C) and D) and E) and A) or G
A
B
C
D
E
F
G
Y
Z
85
Guideline for delay and area minimization
RESULT <= A + B ;
 Try in various design ways
- Proper tradeoff according to design requirement
 Select predesigned adder from component library
- Impossible to change internal structure
- technology dependent
 Add carry lookahead circuit (or coding in VHDL)
- Increased area at least up to 2.5  50%
86
VHDL Evolution and Future(1)


Integration

Need more accurate physical design information.

Ex.: gate delay

Fast reflection on change in ASIC fabrication technology
Tool correctness and performance


Unlimited number of syntheizable entities.
More correct synthesis results from VHDL
source codes.
87
VHDL Evolution and Future(2)

Top level design tool

Formal verification

Date path synthesis

DSP( Digital Signal Processing ) Application

bus-style/pipelined processor

register/register file synthesis
88