Transcript 13 - Electrical and Computer Engineering

Team M1
Enigma Machine
3rd May, 2006
Adithya Attawar (M11)
Shilpi Chakrabarti (M12)
Mike Sokolsky (M14)
Design Manager: Prateek Goenka
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Agenda for Final Presentation
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Title Slide
Project Description
Marketing
Behavioral/Algorithmic Description
Design Process
Floorplan
Issues Encountered
Layout
Verification
Specifications
Conclusions
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Project Description
• Implement on chip the functionality of a World War II
Enigma cipher machine.
• A sophisticated variation on a simple substitution code, it
involves a string of 9 letter pair substitutions, some of
which change for each new character sent through it.
• Must re-create the effect of both the electrical and
mechanical aspects of the device on chip.
• User must be able to change the configuration.
• Each character represented as a 5-bit number.
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Marketing
1) Historical significance
- Complex
electromechanical device
used by Germans
- Was the most secure
communication method
during WWII
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Marketing Cont.
2) Fun Toy!
• Target Audience: 12-18 year olds
• Innovative: Kids can send secret
messages to each other behind their
parent’s back!
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Functional Description
1st step: Plug Board
2nd step: Rotors
3rd step: Reflector
4th step: Rotors
5th step: Plug Board
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Enigma Operation: Plug board
Manually wired and changed
daily
• Daily settings specified in
codebooks given to
operators
• Matched letter pairs (A-J, JA)
• Increased number of
possible machine
configurations by
26*24*22*… = ~1013
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Enigma Operation: Rotors
& Reflector
• 26 spring-loaded
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contacts on each side
Set to an arbitrary initial
position for each
message
Each rotor has unique
internal wiring to perform
letter swaps
Rightmost rotor steps
one notch with each
keystroke, the others
every 26, 262, etc.
Reflector does not move;
hard-wired; swaps letters
and ‘reflects’ signal back
through rotors
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The
Datapath
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Input
Data Reg
Wheel
Position
Counters
Current
Wheel
Counter
Char Reg
5-Bit
Adder
% 26
Plugboard
SRAM
Reflector
ROM
Wheel
shift ROM
Output Reg
10
Input
Data Reg
Wheel
Position
Counters
Current
Wheel
Counter
Step 1: Input Entered
Char Reg
5-Bit
Adder
% 26
Plugboard
SRAM
Reflector
ROM
Wheel
shift ROM
Output Reg
11
Step 2: Plug Board
Input
Data Reg
Wheel
Position
Counters
Current
Wheel
Counter
Char Reg
5-Bit
Adder
% 26
Plugboard
SRAM
Reflector
ROM
Wheel
shift ROM
Output Reg
12
Input
Data Reg
Wheel
Position
Counters
Current
Wheel
Counter
Step 3: Rotor
Char Reg
5-Bit
Adder
% 26
Plugboard
SRAM
Reflector
ROM
Wheel
shift ROM
Output Reg
13
Input
Data Reg
Wheel
Position
Counters
Current
Wheel
Counter
Step 4: Rotor maps new char
Char Reg
5-Bit
Adder
% 26
Plugboard
SRAM
Reflector
ROM
Wheel
shift ROM
Output Reg
14
Input
Data Reg
Wheel
Position
Counters
Current
Wheel
Counter
Step 5: Reflector
Char Reg
5-Bit
Adder
% 26
Plugboard
SRAM
Reflector
ROM
Wheel
shift ROM
Output Reg
15
Input
Data Reg
Wheel
Position
Counters
Current
Wheel
Counter
Step 6: Back through rotor
Char Reg
5-Bit
Adder
% 26
Plugboard
SRAM
Reflector
ROM
Wheel
shift ROM
Output Reg
16
Input
Data Reg
Wheel
Position
Counters
Current
Wheel
Counter
Step 7: Rotor maps new char
Char Reg
5-Bit
Adder
% 26
Plugboard
SRAM
Reflector
ROM
Wheel
shift ROM
Output Reg
17
Step 8: Plug Board
Input
Data Reg
Wheel
Position
Counters
Current
Wheel
Counter
Char Reg
5-Bit
Adder
% 26
Plugboard
SRAM
Reflector
ROM
Wheel
shift ROM
Output Reg
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Design Process
• Initial Design:
• Problem:How to model the Mechanical
behavior of the machine?
• Solution: Use a modular system architecture
with memory used to implement the rotors,
plugboard, and reflector
The Modular nature of the design allows for
flexibility in the number of wheels used and
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the initial position of the wheels.
Design Process
• Design Decisions:
Use a separate ROM for the wheel and
reflector. This allows for 1-bit less in
addressing and removes one clock
cycle from the encryption
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Floorplan
• Initial floorplan
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Final Floorplan
Wheelcounters
Reg3bx8 serialin
Adder_mod26
RAM
RAM
rom26
rom208
Wheelreg_serialin
Fsm
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Final Layout
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Final Layout
Wheel Counters
AddMod26
Reg3bx8 serialin
RAM
RAM
rom208
ROM26
Wheelreg_serial
Fsm
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Metal Rules
• Low-level modules use rules of
directionality as guidelines.
• Use metal 2 sparingly
• High-level modules use metal 2 as short
interconnects, 3 & 4 follow top-level
rules
• Top-level uses metal 2 in any direction,
3 & 4 directions are strictly enforced
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Layer Masks - Poly
Transistor Density: 0.19 per µM2
Density: 8.25%
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Layer Masks - Metal 1
Density: 31.36%
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Layer Masks - Metal 2
Density: 16.96%
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Layer Masks - Metal 3
Density: 12.25%
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Layer Masks - Metal 4
Density: 11.44%
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Verification
• C Code / Behavioral / Structural is easy!!!
• NC Verilog schematic verification also
easy, same results.
• Analog simulations of the entire chip
need to be broken down.
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Module Testing
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Estimated Critical Path
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Estimated Critical Path
Input
Data Reg
Wheel
Position
Counters
Char Reg
5-Bit
Adder
% 26
ExtractedRC
Delay: 3.03nS
Plugboard
Reflector
Max estimated
SRAMclock speed
ROM
of
333 Mhz.
Current
Wheel
Counter
Wheel
shift ROM
Output Reg
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What’s holding it back?
• Worst case adder delay is well over
twice as long as most other cases
A+B
> 25
- 26
• Decoders -> contribute most of the
delay to the SRAM and ROM.
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Pins
PINS
Data Inputs
Control Inputs
Data Outputs
#
16
4
5
Power
2
TOTAL
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Purpose
setting inputs,
character input
clk, set, reset, start
character out
vdd, ground
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Usage
• Set enters the initialization and load
mode. (26 clock cycles)
• Reset clears the current operation and
state, returns to the initialized
settings.
• Newchar starts the encryption cycle,
completes and leaves the value at
charout.
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Specifications
• Total # of transistors: 9247
• Final area: 200 x 253 µM ( 5x10-8 µM 2)
• Maximum clock speed: 333 Mhz
• Average power consumption: 2 mW
• Throughput (3-wheel encryption):
20.8 million characters/second
• How does this compare to our base
case???
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Is it an improvement?
• Some estimates from the original
machine:
• Size: 28 x 34 x 15 cm
• Average power consumption: 130 Watts
• Throughput (any encryption):
2.5 characters/second
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In conclusion
• This new generation enigma encryption
device:
• Is 40,000 times smaller
• Uses 63,000 times less power than the
original
• And runs 7 million times faster
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CitationsRabaey, J. M. et al., Digital Integrated Circuits, Prentice Hall,
2003.
Stojanovic, V. et al., Comparative Analysis of Latches and FlipFlops for High-Performance Systems, ICCD Conference
Proceedings, 1998.
Blanton, S., 18-340 Digital Computation: Fast Adders, Lecture
Notes, 2006.
Enigma Machine, photograph,
www.nsa.gov/gallery/photo/photo00005.jpg
Engima Wheels and Plugboad, photographs,
www.ilord.com/enigma.html
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