Transcript ppt - CRYODET 2

Design ideas
for the MODULAr DAQ
F. Pietropaolo (ICARUS Collaboration)
CRYODET Workshop
LNGS, 14-15 March 2007
Outline
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The ICARUS DAQ design
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Upgraded scheme for MODULAr
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14-15 June 2007
Layout for the T600 detector
Performance and critical issues
Same basic architecture
New components, modularity, cost
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The ICARUS T600 experience
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The T600 DAQ system (5·104 channels), designed in
Padova, engineered and built by CAEN, has proven to
perform satisfactory during the 2001 test run in Pavia.
It consists of a custom designed analogue front-end
followed by a multiplexed AD converter and by a digital
VME module performing local storage, hit finding and
data compression.
From the experience gained with the T600, we
propose a natural evolution, based on the same basic
architecture, for a DAQ suitable for multi-kton
detectors with >> 105 channels (more performing
components, larger integration, lower cost).
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The ICARUS read-out principle
m.i.p. ionization
~ 6000 e-/mm
Time
Edrift ~ 500 V/cm
Drift direction
Hit
finder
Mux
8:1
Low-noise
amplifiers
Front-end
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FADC
Memory
400ns
n x 4kB
multi-event
circular buffer
Continuous
waveform
recording
To storage
Daedalus
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The induction signals
Electrons
path
Ionizing track
Induced current
Edrift
Induced charge
T=0
Drift
u-t view
E1
Induction 1
v-t view
d
E2
Induction 2
w-t view
Charge
= area
d
Collection
Charge
= ampl.
p
Drift time
Drift time
• ICARUS T600: three wire planes (pitch 3mm, separation 3mm)
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Edrift = 500 V/cm
Mip signal ~ 12000 e- (inc. recombinantion)
Electron drift velocity ~ 1.5 mm/s
Typical grid transit time ~ 2-3 s
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Preamplifier for LAr TPC
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Need of very low noise amplifier:
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No amplification around sense wires
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Large input capacitance (CD)
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Induced charge ~ 104 electrons
Wires (20 pF/m) + cables (50 pF/m)
In T600 CD ~ 300-400pF
Serial noise (proportional to CD)
dominates over parallel noise
(proportional only to signal
bandwidth)
High trans-conductance (gm) input
device is required to ensure
acceptable Signal-to-Noise level
(S/N ~ 10)
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esn 
2
S /N 
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gm
q
CF
q


CF esn  CD esn  CD
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Choice of the active input device
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Bipolar transistors
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VLSI-CMOS
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gm ≈ 400mS @ Ic ≈ 10 mA (Amplification merit factor gm·Zout ≈ 3-4·105)
BUT: parallel noise density ≈ 2 pA / √Hz too high (with a typical LAr
signal bandwidth of ~ 1 MHz gives unacceptable noise contribution)
Extremely low gm
jFET
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Good gm ≈ 40mS @ Ids ≈ 10 mA (Amplif. merit factor gm·Zout ≈ 3-4·104)
negligible parallel noise density ≈ 0.001 pA / √Hz
ICARUS choice since 1986:
charge sensitive preamplifier with high gm jFET input stage
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The ICARUS T600 preamplifier
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Custom IC in BiCMOS technology
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Classical Radeka integrator
External input stage jFET’s
 Two IF4500 (Interfet) or
BF861/2/3 (Philips) in parallel
Two versions:
“quasi-current” mode: RfCf ≈ 1.6s (collection +
first induction)
“quasi-charge” mode: RfCf ≈ 30s (mid induction)
Cz
R2
R1
to increase gm (50-60 mS)
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External feed-back network
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Allow sensitivity and decay time
optimization
High value f.b. resistor (100M)
reduce parallel noise
BW noise reduction
Two channels per IC
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Identical symmetrical layout
guarantees identical electrical
behavior
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R3
Cu
External baseline restorer circuit
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R4
Cs
Rf
Ra
Cf
AGND
Rp
Sensitivity ≈ 6 mV/fC
Dynamic range > 200 fC
Linearity < 0.5% @ full scale
Gain uniformity < 3%
E.N.C. ≈ (350 + 2.5 x CD) el ≈ 1200 el. @ 350pF
Power consumption ≈ 40 mW
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Layout of front-end electronics
UHV
Feed-through
(18x32ch.)
Liquid argon
H.V. (<±500 V)
VME board (18/crate)
Gas
Sense wires
(4-9m, 20pF/m)
4 Multiplexers
(400ns x 8ch.)
Twisted pair cables
(~5m, 50pF/m)
Decoupling
Boards
(32 ch.)
Front-end
amplifiers
(32/board)
F
A
D
C
10bit FADC
50ns sampling
1mV/ADC
(~1000e-/ADC
matches el. Noise)
ICARUS T600: ~ 54000 channels — 1720 boards — 96 crates
Cost of the full electronic chain: ~ 120 € / channel
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The ICARUS T600 read-out chain
CAEN-V789 board: 2 Daedalus VLSI * 16 input channels
(local self-trigger & zero suppression) + memory buffers +
data out on VME bus
Signal UHV feed-through:
576 channels (18 connectors x 32)
+ HV wire biasing
CAEN-V791 board: 32 pre-amplifiers +
4 multiplexers (8:1) + 4 FADC’s (10 bits - 20 MHz)
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Decoupling board:
HV distribution and
signal input
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The T600 electronic racks
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The analogue board V791
FADC’s
Multiplexers
Digital link
Preamplifiers
QuickTime™ and a
TIFF (Uncompressed) decompressor
are needed to see this picture.
BiCMOS
IC layout
Input signal
connector
Output of
analogue sum
Shielding of
front-end
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Analogue board block diagram
32 channel module
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Signals from the LAr-TPC
Wire numbering (2.54mm pitch).
Image of a low energy electromagnetic shower
m.i.p. ≈ 12 ADC counts
(3 mm) FWHM ≈ 5 µs
Drift time (400ns sampling).
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Noise ≈ 1.3 - 1.7 ADC counts rms
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The digital board (ARIANNA)
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Receives 32 channels data
stream through the serial link
Hosts two custom made feature
extraction ASIC chips
(DAEDALUS) for hit finding, zero
skipping and self triggering
Complies with VME standards
Each DAEDALUS operates on
16 channel data stream and
controls the circular memory
multi-buffers. It includes a
median filter to reduce high freq.
noise
A 28 bit absolute time register is
associated to each buffer in
memory to allow alignment of
data in event reconstruction
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On-line data reduction
Raw data
(one T600 event = 200 Mb)
DAEDALUS chip
V791
BOARD
V789
BOARD
EVENT
FIFO
EXT.
TRIGGERS
DAEDALUS
CHIPS
2 • 16 ch
CKSYNC
8 ANALOG
CHANNELS
MUX
8:1
ADC
LINK
RAM
Reduced data
CLK
20 MHz
Daedalus feature:
Varying rise-time
front-edge finder
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T600 DAQ throughput
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The T600 DAQ is based on VME standard for Digital boards
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best choice at time of design in term of throughput (~40 Mbyes/s).
For the analogue boards the same 6U Eurocard standard was adopted, with
a custom backplane to connect the inputs from wires and distribute common
signals (ADC baseline bias, enable signals, test pulses, etc.).
In the T600 DAQ, 18 ARIANNA boards are housed in one VME crate that
serves a total of 576 channels.
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One crate is connected to an analogue crate with the same modularity which
in turn receives the signals from a single T600 flange (18 feed-through
connectors, each hosting 32 channels).
Configuration and control of the 18 boards relies on a dedicated VME CPU,
which also handles the data transfers from board buffers to the Ethernet
event builder network.
Performance of the DAQ system is bounded by the VME slave ARIANNA
interface throughput (8-10 MB/s equivalent to few Hz full drift collection).
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Critical issues for scaling up
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The T600 DAQ was conceived in 1997:
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The front-end dual channel BiCMOS and the DAEDALUS circuits
were designed on 1998
The full 5 104 channels system was built, tested and mounted on
the T600 by 2001
The architecture has proven to be reliable and performing
But: impossible to replicate on larger scale because main basic
components are discontinued
The scaling up of the ICARUS DAQ to fit MODULAr
requirements is based on:
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A detail analysis of the whole system to spot the areas where
necessary changes could lead to a more efficient structure
An in-depth revision of the DAQ design in term of new components
available on the market, channel number (>>105) and cost (aiming
at < 60 €/channel)
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Signals and noise in MODULAr
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In a multi-kton TPC we can foresee wires with a pitch larger than
the 3mm used in the T600
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The adoption of 6mm pitch for MODULAr seems reasonable and will
permit to use most of the existing molds and tools for wires support.
The capacitance associated to each channel will be determined by
the capacitance of the wires, in the order of 20pf/m, in parallel with
the capacitance of the cable, in the order 50pF/m.
A realistic value for 10m electrode wires, 6mm pitch, and average
8m of cable is a capacitance of ~600pF (cfr.: 300-400pF in the
T600)
It follows that the Signal to Noise Ratio from the MODULAr wire
chambers should be very similar to that of the T600.
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Hence a completely new design of the analogue front-end would
hardly improve the performance being the present design already
optimized for large input capacitance.
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The pre-amplifier
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In the ICARUS custom IC we integrated two
identical channels.
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This choice was due to the use of an external input
active devices (jFET), the feedback network and the
integrating capacitor.
Limitation to two channels makes possible an
identical symmetrical layout with an identical
behavior for the two channels.
Prototype of a four channel
amplifier and BW filter based
on the new package IC.
Following this solution, fully satisfactory in the
T600, only the amplifier packaging has been
reviewed.
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This component is already available and more than
105 dies on sealed silicon wafers are also available.
This new smaller package allows a higher degree of
integration.
First measurements, made on available prototypes,
show performance similar to that of the T600
packaging.
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New package
Original used in T600
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AD conversion
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Serial ADC are preferable over Flash ADC.
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They provide the converted data as a sequence of bits at high
rate. The data rate of the serial bits is typically around 10-12
times higher than sampling frequency. For instance to reach the
3MHz sampling rate, AD7273 must be clocked at 48MHz.
These devices are quite interesting for price, power consumption
and dimensions. Typically they are packed in Mini Small Outline
Package (MSOP) smaller than 5x5 mm2.
The choice is rather large and we can expect that more products
will be available within one year.
The acceptable sampling frequency for a TPC with 6 mm pitch
can be assumed in the range of 1–2Mhz for which there is
already a wide choice of devices.
We can assume a resolution of 10bit but 12bit ADCs are also
available at reasonable cost.
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Available Serial ADC
Manufacturer
Res
Part. Num.
Freq.
MHz
Power
mW typ.
Supply
Cost $ 1000 pcs
Analog Devices
10
AD7273
3
11.4
2.35 – 3.6
3.75
Analog Devices
10
AD7277
3
10.5
2.35 – 3.6
3.60
Maxim
10
MAX1334
4.5
40
5, 3.3
NA
Maxim
10
MAX1335
4
40
3.3
NA
Analog Devices
12
AD7274
3
11.4
2.35 – 3.6
3.75
Analog Devices
12
AD7276
3
10.5
2.35 – 3.6
4.0 – 6.25
Linear Technology
12
LTC1403-1
2.8
14
2.7 – 3.3
4.00
Maxim
12
MAX1332
3
38
5, 3.3
NA
Linear Technology
14
LTC1403A-1
2.8
14
2.7 – 3.3
7.00
Analog Devices
16
AD7621
3
86
2.5
29.95
The frequency given in the table refers to the sampling rate.
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New front-end layout
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The whole front-end can be hosted in a
compact crate very close to the feedthrough flange.
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A solution is under study with the feedthrough flange as a backplane supporting
the analogues boards that host amplifiers
for 576 channels.
The number of connectors and cables
would be drastically reduced with a benefit
for cost and S/N.
The new DAQ modularity is defined by
the channels served by one flange (576).
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This new module, replacing the old
analogue board (modulo 32), will also
perform digitization before streaming data
to the digital buffering board.
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The new data distribution
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A set of a few FPGA for 576 channels will be used to handle,
filter, and organize the serial information provided by the serial
ADC’s.
Assuming a sampling frequency of 1.5Mhz, 10bit ADC’s and data
compression in one byte, we need to transmit ~8 Gbit/s,
(including error correction redundancy).
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Optical links with 1.5Gbit/s data rates are standards and can be
driven by the Rocket-IO™ interfaces available on many FPGA from
different vendors.
Six optical links could serve all the channels of one module (576)
and convey also extra information as absolute time.
Some of the links will be bidirectional to distribute absolute clock
and simple commands.
The ADCs and FPGA’s will be housed in the same crate next to
the flange or on special boards on top of the amplifiers boards.
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Amps and AD module
576 channel module
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Digital I/O
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What has not been discussed is the implementation
of the equivalent of the ARIANNA board.
One could say that, nowadays, ASIC VLSI will not be
required for hit finding as all the feature extraction and
TRIGGERING algorithms can be implemented in powerful
FPGA
The architecture of the DAQ system can be enhanced through
the adoption of a modern switched I/O, as PCI Express, allowing
the parallelization of the data flows.
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Such I/O transaction can be carried over low cost optical gigabit/s
serial links.
This allows a more effective modularity of the digital hardware
architecture, decoupled from the geographical distribution of the
signal feed-throughs, thus lending to a larger integration and the
consequent lower cost per channel.
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Summary
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The ICARUS DAQ basic architecture is well
suited even for larger size LAr-TPC
An in-depth revision of the project based on new
modern components and aiming at lower cost
(less than 60 € / channel) is underway
Main upgrades concern:
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Higher integration of the front-end amplifier
Adoption of high frequency serial ADC
Use of powerful FPGA for data filtering and distribution
Optical link for Gbit/s transmission rate
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