Transcript Lecture #3 - Dr.Nazar Abbas Home Page

FPGA Based System Design
Lecture 3: Introduction to FPGAs
Dr. Nazar Abbas Saqib
NUST Institute of Information
Technology (NIIT)
[email protected]
We will discuss..
• Programming Architectures
• Historical Perpective
• PALs, PLDs, CPLDs & FPGAs
Pl note source of the figures included in this lecture
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Historical Perspective
1945 1950 1955 1960 1965 1970 1975 1980 1985 1990 1995 2000
Transistors
ICs (General)
SRAMs & DRAMs
Microprocessors
SPLDs
CPLDs
ASICs
FPGAs
1. First programmable logic devices to appear in 1970
2. Can implement any set of sum of the product logic equations
SRAMs, DRAMs & Microprocessors
1.
2.
3.
4.
5.
Late 1960s and early 1970s – New development in technology
Intel introduced first 1024 bit DRAM in 1970 (the 1103)
Fairchild introduced first 256-bit static RAM in 1970 (the 4100)
Intel also introduced first Microprocessor in 1971 (the 4004)
Our intrest: Most of today FPGAs are SRAM based with
embedded microprocessors
PLD (Programmable Logic Devices)
1. The first programmable ICs were generally refered to as PLDs
2. They are grouped as
• SPLDs : Simple PLDs
• CPLDs: Complex PLDs
3. SPLDs being less sophisticated, less logic
• The firs programmable chip comes in the form of PROM in 1970s
4. CPLDs being more complex, late 1970s and early 1980s
• MegaPAL from MMI in 1984
PLDs
SPLDs
PROMs
PLAs
CPLDs
PALs
GALs
etc.
PROM (Programmable ROM)
1. The first simple PLD
2. Prefined AND array, programmable OR array
b
c
Predefined link
Programmable link
Address 0
&
Address 1
&
Address 2
&
Address 3
&
Address 4
&
Address 5
&
Address 6
&
Address 7
&
!b
c
!c
Predefined AND array
!a & b & c
a & !b & !c
a & !b & c
a & b & !c
a & b & c
l
b
!a & b & !c
l
!a
!a & !b & c
l
a
!a & !b & !c
Programmable OR array
a
w
x
y
PROM (Programmable ROM)
b
c
Predefined link
Programmable link
Address 0
&
Address 1
&
Address 2
&
Address 3
&
Address 4
&
Address 5
&
Address 6
&
Address 7
&
!a & !b & !c
!a & !b & c
!a & b & !c
!a & b & c
a & !b & !c
a & !b & c
a & b & !c
a & b & c
w = (a & b)
x = !(a & b)
y = (a & b) ^ c
l
Programmed PROM
Lighter, cheaper, fast logic
l
Predefined AND array
l
a !a b !b c !c
•
•
Programmable OR array
a
w
x
y
PLA (Programmable Logic Arrays)
a
Programmable AND array, programmable OR array
b
c
Predefined link
Programmable link
&
&
&
Predefined AND array
l
!c
N/A
l
c
N/A
l
a !a b !b
N/A
w
x
y
Programmable
OR array
•
PLA (Programmable Logic Arrays)
b
c
Predefined link
Programmable link
&
&
&
a & b & c
a & c
!b & !c
x = (a & b & c) | (!b & !c)
y = (a & b & c)
l
w = (a & c) | (!b & !c)
l
Predefined AND array
l
a !a b !b c !c
w
x
y
Programmable
OR array
a
PAL (Programmable Array Logic)
GAL (Generic Array Logic)
1. Exactly opposite to PROM
2. Programmable AND arrays, predefined OR arrays
3. Address speed issues in PLAs
a
b
c
Predefined link
Programmable link
Predefined OR array
&
&
&
&
&
&
a !a b !b c !c
l
l
l
Programmable
AND array
w
x
y
CPLDs (Complex PLDs)
1.
2.
3.
4.
An array of PLDs
Global routing resources
From PLD to other PLDs
Example: Cypress 39K
ASICs (Application Specific
Integerated Circuits)
ASICs
Gate
Arrays
Structured
ASICs
Standard
Cell
Increasing complexity
Full
Custom
The Gap between PLDs & ASICs
1. PLDs : Programmable but less complexity
2. ASICs: High complexity but no programmability
PLDs
SPLDs
CPLDs
ASICs
The
GAP
Gate Arrays
Structured ASICs*
Standard Cell
Full Custom
*Not available circa early 1980s
IOB
IOB
IOB
IOB
CLB
CLB
CLB
CLB
IOB
CLB
IOB
CLB
IOB
IOB
Input/Output
Block
IOB
FPGA Structure
IOB
SM
CLB
SM
CLB
IOB
SM
CLB
SM
CLB
SM
IOB
Configurable
Logic
Block
CLB
SM
SM
CLB
SM
SM
CLB
CLB
CLB
CLB
IOB
IOB
IOB
IOB
Typical Capacity : 5 million to 1 billion transistos
Switch
Matrix
FPGA Structure
• Three main components
• Configurable Logic Blocks (CLB)
• Programmable I/Os
• Programmable Interconnects (Switch
Matrix)
The CLB is the most important component of FPGA structure
Configurable Logic Block (CLB)
Configurable logic block (CLB)
Slice
CLB
CLB
Logic cell
Logic cell
Slice
CLB
CLB
Logic cell
Logic cell
1. 2-D array of CLBs
2. Each CLB consists of 2 slices
CLB Slice
Slice
16-bit SR
Logic Cell (LC)
16x1 RAM
4-input
LUT
LUT
16-bit SR
MUX
REG
Logic Cell (LC)
16x1 RAM
4-input
LUT
LUT
MUX
REG
1. Each slice has 2 logic Cell (LC)
2. Each Logic cell comprises a LUT, and some additional components i-e
Multiplexers, Registers
FPGA CLB Slice (Internal View)
mux Based CLB (Altera)
AND
a
&
b
OR
|
c
y
y = (a & b) | c
0
0
b
1
MUX
0
a
y
1
0
x
1
MUX
0
0
0
1
1
c
MUX
MUX
1
LUT Based CLB (Xilinx)
a
b
c
Truth table
&
|
y = (a & b) | !c
y
Programmed LUT
a b c
y
SRAM cells
0
0
0
0
1
1
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
000
001
010
011
100
101
110
111
8:1 Multiplexer
Required function
abc
y
LUT Based CLB – How to load SRAM cell
Transmission gate
(active low)
11
00
Transmission gate
(active high)
11
SRAM
cells
11
y
11
00
11
11
c
b
a
LUT Based CLB – How to load SRAM cell
From the previous
cell in the chain
1
0
0
0
To the next cell
in the chain
SRAM
cells