Transcript jeita - DASC

JEITA EDA-TC updates
IEEE-DASC meeting at SystemC Japan2010
1st July, 2010
at Cadence Japan Office
JEITA EDA Technical Committee, Fellow
IEC TC93 WG2, Co-convener
NEC System Technologies
Satoshi Kojima
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- Outline 
Updates since DVCon2010 meeting

EDA-TC structure and STD-TSC activities

LSI-Package-Board co-design Working Group

Summary

Appendix

Collaboration scheme w/IEC and IEEE

Design language harmonization

BVDL: the Bird’s-eye View for Design Languages
IEEE-DASC at SystemC Japan2010, 01Jul2010
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© Copyright 2010 JEITA
Copyright(C) JEITA 2008
JEITA Structure and Management
JEITA
Japan Electronics and Information Technology Industries Association
Policy and Strategy Board
Environment Board
Consumer Electronics Board
IT and Industrial Systems Board
Display Devices Board
Electronic Components Board
Semiconductor Board (JEITA-JSIA)
Semiconductor Industrial Affairs Committee
Semiconductor International Affairs Committee
Semiconductor Technology Committee
Marketing Committee
Road Map Committee
EDA Technical Committee (EDA-TC)
- Member : 1４ Companies
Fujitsu SL, Panasonic, Toshiba, Renesas, Sony,
Synopsys, JEDAT, Mentor, Ricoh, Zuken Elmic,
Newly joined…DENSO, NEC, CANON,
NEC TOPPAN Circuit Solutions
IEEE-DASC at SystemC Japan2010, 01Jul2010
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EDA-TC Structure in Fiscal Year 2010
EDA Technical Committee
Chair: Yoshida (Renesas)
Acceleration of Standardization
EDA Standardization Technical Sub-Committee
Chair : Imai (Toshiba), Vice-chair : Kawamura (Fujitsu SL)
SystemC Working Group
Kojima (NECST)
Chair : Imai (Toshiba)
LSI-Package-Board Co-design Working Group
Chair : Fukuba (Toshiba)
Solution for Technical Challenges
NPD (Nano-scale Physical Design) Working Group
Chair: Tanaka (Panasonic)
Promotion of EDA Technology
EDSFair 2011 Executive Committee
Chair : Ohta (Panasonic)
IEEE-DASC at SystemC Japan2010, 01Jul2010
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EDA Standardization TSC Activities
Members: semiconductor vendors, EDA vendors and
academia



Chair: Imai (Toshiba)
Vice-chairs: Kawamura (Fujitsu SL), Kojima (NECST)
To reflect opinions on technical and business issues as a
group of EDA power users to De Jure standard bodies such
as IEEE and IEC TC93

To raise issues on design flows to solve today and future
design challenges from the member companies and to
propose what standards can contribute to solve them


Two subsidiaries are actively working


SystemC Working Group
LSI-Package-Board Co-design Working Group
IEEE-DASC at SystemC Japan2010, 01Jul2010
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SystemC Working Group


To standardize design language and its subsidiaries of synthesis
and verification to support ESL design methodology
Member : SystemC Experts from 8 Companies



Chair: Imai (Toshiba)
Fujitsu, Panasonic, Mentor, Renesas, Sony, Synopsys, Toshiba, Ricoh
Current activities:
Work with IEEE P1666-WG to contribute SystemC-2010 standards
to add TLM 2.0 features and correct SystemC-2005 errata

Execute survey on SystemC, and share the result with other regional
SystemC User Group (World-Wide). Continue the survey in SystemC
Japan 2009 and 2010 after deciding no System Design Forum in
conjunction with EDSFair2010

IEEE-DASC at SystemC Japan2010, 01Jul2010
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LSI-PKG-Board Co-design Working Group
A new WG was formed and to aims harmonization for codesign environment among LSI, Package and Board in April,
2010 after Fukuba-san in Toshiba and his team had intensively
discussed since summer 2009.


Member : 24 Experts from 16 Companies and academia
Chair: Fukuba (Toshiba), Vice-chair: Takana (SONY)
 Fujitsu SL, SONY, Renesas, Panasonic, Toshiba, Zuken,
Ricoh, Mentor, Denso, CANON, NEC, NEC Toppan Circuit,
Fujitsu VLSI, Appach, Ansoft, ATE Service, Shibaura Inst. of Tech.

To describe and share technical issues to establish co-design
environment among LSI, Package and Board
 To propose shared common data base and/or data format
which might classify into 3 data types such as shape,
netlist/circuit and technology

IEEE-DASC at SystemC Japan2010, 01Jul2010
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Summary

Talked about update of EDA-TC organization chart in FY2010
New working group, LSI-PKG-Board Co-design WG, was
formed in April, 2010

EDA-TC member expanded System companies, PKG/Board
companies and PKG/Board EDA companies in addition to
Semiconductor and SoC EDA companies

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Collaboration w/IEEE and IEC

Domestic collaboration

To dispatch a chair and some experts to WG2 of IEC TC93 JNC in IEICE
(The Institute of Electronics, Information and Communication Engineers)
and to lead the activities of the WG2 JNC

Global collaboration
Worked with P1800WG (SystemVerilog), P1666WG (SystemC) and
P1801WG (Power format) in IEEE-DASC, reviewing the drafts and
participating in the balloting. Planning work with P1481(SSPEF)
 Has been a member of IEEE-SA since 2004 and participated in balloting
such as IEEE1800, IEEE1666 in 2005 and IEEE1801 in 2008
 Kojima has been a JEITA DR of IEEE DASC since 2008
 Kojima has been a Co-convener of TC93 WG2 since 2000 and worked
with Dennis Brophy in USNC
 IEEE-IEC Dual Logo agreement made in 2003 accelerates EDA global
standardization such as SytemC, System Verilog…

IEEE-DASC at SystemC Japan2010, 01Jul2010
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Copyright(C) JEITA 2008
Collaboration scheme
IEC
IEICE
TC93 JNC
TC93 Int’l
Representatives
WG2
WG2 JNC
Dual Logo agreement
IEEE
JEITA
EDA-TC
CAG
IEEE-SA
NesCom, RevCom
DASC
Membership
EDA STD-TSC
WG2 JNC
SC-WG
PF-WG
NPD-WG
IEEE-DASC at SystemC Japan2010, 01Jul2010
WGs (P1666, P1801,
P1481, …)
Hand-offs
Accellera, OSCI
Collaboration
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JEITA to set strategies of EDA standards
EDA standards provide
a mechanism for defining common
semantics for integrated design
systems among various tools
System
Design

Verification
Specification
(Function + Constraints)
To define common SoC design
flow and then categorize existing
and emerging standards

Implement w/Opt.
Analyze
Software
Area
Logic
Timing
Equivalence check
To set strategies of EDA
standardization activities
for every category

Function
Performance
Testability
Scan/BIST
Communicate
Circuit
Place
Route
Power
Noise
Libraries
DFT
DFM
Data for manufacturing
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Design languages harmonization
JEITA had some good lessons-learned through power format
standardization activities under 2 formats issues of UPF and CPF
 Criteria to qualify De Jure standard is applicable for practical
SoC design flow or not
 Unification is best, but in reality interoperability and
harmonization are indispensable

An AMS language is derived from a digital design language to
cover digital- analog mixed signal world. In result, there are three
AMS languages in an EDA community
 VHDL-AMS is IEEE standard and might be in an academia
 Verilog-AMS might be De Facto standard in the market
 SystemC-AMS will be OSCI standard soon

IEEE-DASC at SystemC Japan2010, 01Jul2010
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Copyright(C) JEITA 2008
Bird’s-eye view for Design Languages
BVDL aims to make full use of planning and decision-making on
JEITA activities and to facilitate global understanding of various
design languages, classified into De Jure standards, Forum
standards and De Facto standards

BVDL is a set of charts to show the position that each design
language occupied in the design technology along a generally
accepted design flow
 The X-axis shows design phases of the flow
 The Y-axis shows design objects which is a set of design
data such as hardware description, verification description,
design constraints and so on


Current status
 We have created the first version of BVDL
 We will use it for upcoming 2010 fiscal year planning
IEEE-DASC at SystemC Japan2010, 01Jul2010
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Copyright(C) JEITA 2008
How to read BVDL. Design flow (X-axis)
The X-axis of BVDL’s chart corresponds to design flow.
The languages used in each design step of the flow are shown.
Design Flow (X-Axis)
BVDL
Analog Functional Design
Post-Layout Circuit
Analog Architecture Design
Verification
Design Process
Mixed-Signal Verification
3.2 Mixed-Signal Verification
3.1 Analog Block Design
Post-Layout Circuit Verification
Layout Design
Transistor-Level Circuit Design
Analog Functional Design, Architecture Design
Objects
Structure
Logical Behavior & Function
Logical Behavior & Function - Extended for AMS
Analog　Behavior & Function
Gate-Level
Circuit languages that are
Design
IEEE-DASC at SystemC Japan2010, 01Jul2010
FSDB
Hardware
Hardware
Hardware
Hardware
Hardware
IEEE #
IEC #
SPICE
SoC
SoC
SoC
SoC
SoC
VHDLーAMS
Description Objects
Object Group
VerilogーAMS
Design
Language
ー
ー
ー
ー
X
X
X
X
X
X
X
X
X
X
“Analog Functional
used in
Design, Analog Architecture Design” phase are shown here.
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How to read BVDL. Design objects (Y-axis)
The Y-axis of BVDL’s chart corresponds to design objects.
The design objects that are defined in each language are marked
with a cross.
BVDL　Design - Manufacturing Interface
Sign-off Verification
Place-and-Route
Logic (Gate-level) Verification
Logic (Gate-level) Synthesis
RTL Design & Verification
High-Level Design & Verification
Objects
Structure
Logical Behavior & Function
Gate-Level Circuit
Timing Constraints
Power Structure
Floor plan
Place-and-Route Data
Layout Data
Test Bench
Property
Assertion
Functional Coverage
Transactor
Test Pattern
Random Verification15
1666
X
X
X
© Copyright 2010 JEITA
X
VHDL
SoC Hardware
SoC Hardware
SoC Hardware
SoC Hardware
SoC Hardware
SoC Hardware
SoC Hardware
SoC Hardware
Functional Verification
Functional Verification
Functional Verification
Functional Verification
Functional Verification
Functional Verification
IEEE-DASC at
SystemCVerification
Japan2010, 01Jul2010
Functional
IEEE #
IEC #
Verilog
Description Objects
Object Group
SystemVerilog
Design
Language
SystemC
Design Objects (Y-Axis)
2. SoC Design
Design Process
1800
62530
X
X
X
1364
61691ー4
X
X
X
1076
62248
X
X
X
X
X
X
X
X
X
X
X
X
X
X Copyright(C) JEITA 2008
BVDL consists of four charts.
To make BVDL easy to grasp, we divided BVDL into four charts.
Each chart corresponds to one of the four major design processes.
BVDL (Four charts)
設計言語俯瞰図
設計工程
1. システム･レベル設計
PWB（Printed Wiring Board）設計、パッケージ設計
アーキテクチャ設計、アルゴリズム設計
要求分析、仕様定義
設計言語俯瞰図　2. SoC設計
X
X
CDL
X
X
1076
62248
X
IPーXACT
X
X
1364
61691ー4
X
OASIS
2. SoC Design
X
X
1800
62530
X
Liberty
X
IEEE #
IEC #
LEF
X
X
X
X
X
X
X
X
X
X
X
X
X
GDS II
X
X
X
X
X
X
X
VHDL
X
構成
論理動作・機能
論理動作・機能ーAMS拡張
アナログ動作･機能
ゲート･レベル回路
トランジスタ･レベル回路
タイミング制約
電源構造
フロアプラン
配置配線データ
レイアウトデータ
テストベンチ
テストベンチーAMS拡張
プロパティ
アサーション
機能カバレッジ
トランザクタ
テストパターン
ランダム検証
論理・回路シミュレーション結果
配線寄生容量
配線寄生抵抗
配線を構成する端点座標
LVS用ネットリスト
遅延時間
素子特性（Sパラメータ、他）
小分類
Verilog
X
X
X
X
X
X
X
X
小分類
SoCハードウェア
SoCハードウェア
SoCハードウェア
SoCハードウェア
SoCハードウェア
SoCハードウェア
SoCハードウェア
SoCハードウェア
SoCハードウェア
SoCハードウェア
SoCハードウェア
機能検証
機能検証
機能検証
機能検証
機能検証
機能検証
機能検証
機能検証
EDAツール間インターフェース
EDAツール間インターフェース
EDAツール間インターフェース
EDAツール間インターフェース
EDAツール間インターフェース
EDAツール間インターフェース
素子特性
記述対象物
大分類
ライブラリ、コンポーネント･モデル
論理ライブラリ･モデル
ライブラリ、コンポーネント･モデル
配置配線用ライブラリ･モデル
ライブラリ、コンポーネント･モデル
レイアウトデータ
ライブラリ、コンポーネント･モデル
遅延計算モデル
ライブラリ、コンポーネント･モデル
LVS用ネットリスト
IP
IPメタデータ
SystemVerilog
X
1364
61691ー4
X
X
X
GDS II
X
1800
62530
X
X
X
OASIS
X
ー
ー
CITI
X
1850
62531
ー
ー
Open Access
X
X
X
1647
FSDB
X
X
X
X
X
X
X
1801
ー
ー
TouchStone
1076
62248
X
X
X
ー
ー
X
SPICE
1364
61691ー4
X
X
X
VerilogーA
1800
62530
X
X
X
IEEE #
IEC #
VHDLーAMS
X
X
記述対象物
大分類
VerilogーAMS
Design Process
キャラクタライズ
設計言語
Verilog
1. Electronic System Design
1666
FSDB
X
IEEE #
IEC #
SystemVerilog
X
X
小分類
構成
論理動作・機能
ゲート･レベル回路
タイミング制約
電源構造
フロアプラン
配置配線データ
レイアウトデータ
テストベンチ
プロパティ
アサーション
機能カバレッジ
トランザクタ
テストパターン
ランダム検証
論理･回路シミュレーション結果
配線寄生容量
配線寄生抵抗
配線を構成する端点座標
LVS用ネットリスト
遅延時間
バウンダリスキャン回路
テストデータ
コアテスト
圧縮スキャン構造
e
X
記述対象物
大分類
SoCハードウェア
SoCハードウェア
SoCハードウェア
SoCハードウェア
SoCハードウェア
SoCハードウェア
SoCハードウェア
SoCハードウェア
機能検証
機能検証
機能検証
機能検証
機能検証
機能検証
機能検証
EDA:ツール間インターフェース
EDA:ツール間インターフェース
EDA:ツール間インターフェース
EDA:ツール間インターフェース
EDA:ツール間インターフェース
EDA:ツール間インターフェース
SoCテスト
SoCテスト
SoCテスト
SoCテスト
PSL
X
UPF
X
CPF
X
VHDL
X
X
Verilog
X
X
設計工程
IPモデル作成
4. キャラクタライズ、IP化
ポストレイアウト回路検証
レイアウト設計
トランジスタ・レベル回路設計
機能設計、アーキテクチャ設計
設計言語
設計言語
1149.1b
ー
設計言語俯瞰図
設計工程
ミックスド・シグナル検証
3.2 ミックスド・シグナル検証
3.1 アナログ･ブロック設計
SystemC
X
ー
62014
X
X
X
X
X
X
X
設計言語俯瞰図
設計工程
設計・製造インタフェイス
サインオフ検証
Place-and-Route
論理検証
論理合成
RTL設計・検証
高位設計･検証
SystemVerilog
X
X
BSDL
1666
CITI
P1699
TouchStone
P1778
IBIS
Rosetta
SystemC
IEEE #
IEC #
SystemCーAMS
小分類
構成
論理動作・機能
論理動作・機能ーAMS拡張
性能・特性
性能・特性ーAMS拡張
検証用記述
検証用記述ーAMS拡張
I/Oバッファ特性
バウンダリスキャン回路
素子特性（Sパラメータ、他）
UML
記述対象物
大分類
電子機器システム
電子機器システム
電子機器システム
電子機器システム
電子機器システム
電子機器システム
電子機器システム
SoCハードウェア
SoCテスト
素子特性
Esterel
設計言語
1685
X
X
X
X
X
X
X
X
3.1 Analog Block Design
3.2 Mixed-Signal Verification
X
X
X
X
X
X
4. Characterization,
IP Preparation
Electric System
Manufacturing
1. Electronic System Design
4. Characterization / IP Preparation
2. SoC Design
3.1 Analog Block Design
IP Development
(Subset of SoC Design Process)
3.2 Mixed-Signal Verification
SoC Manufacturing
IEEE-DASC at SystemC Japan2010, 01Jul2010
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Copyright(C) JEITA 2008
The Four Major Design Processes
Electronic System Design
Electronic System Design is a design process to develop electronic
systems.
The Electronic System Design chart of BVDL describes interface with
SoC design mainly.
This is because JEITA EDA-TC’s activity is primarily for
semiconductor industry.
SoC Design
SoC Design is a design process to develop System-on-Chips.
The SoC Design chart of BVDL describes only digital part of SoC
design.
This is to make the chart easy to understand.
Analog circuits are developed in the Analog Block Design process
and are imported as blocks.
This is not always true. But it is NOT worthy to create a perfect
definition of total design process for our purpose.
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Copyright(C) JEITA 2008
The Four Major Design Processes
(cont’d)
Analog Block Design / Mixed-Signal Verification
Analog Block Design is a design process to develop analog blocks.
The blocks developed in this process are provided to the SoC design
flow through “Characterization / IP Preparation” process.
Mixed-Signal Verification is the process to verify the interface
between the digital portions and the analog portions.
Characterization / IP Preparation
“Characterization / IP Preparation” is a design process to prepare
data of analog blocks and IPs.
The prepared data in this process are provided to other design
processes.
The languages for the interface data are collected, but the definitions
of this process is under discussion now.
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Copyright(C) JEITA 2008
How to use BVDL.
Example-1.
Case
Two languages exist in the same design phase and define
the same design objects.
Example: UPF and CPF
Action Candidates.
Clarify the difference of the languages.
Minimize the obstacles to keep interoperability of the
languages.
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How to use BVDL.
Example-2.
Case
Technology shift from lower level to higher level.
Example: “RTL Compile” and “C Compile”
Action Candidates.
Learn from old technology and make plan for new technology.
RTL Compile (Old Technology)
Style Check
Design Descriptions
(RT-Level)
Design Constraint
(SDC, UPF)
RTL Compile
Equivalence Check
Design Descriptions
(Gate-Level)
Constraint Check
C Compile (New Technology)
Do we define the design description language enough for C compile
and Equivalence Check?
Are design constraint languages ready for practical purposes?
IEEE-DASC at SystemC Japan2010, 01Jul2010
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Copyright(C) JEITA 2008
Future Plan
Today, we introduced our BVDL as one of our activities.
Purpose.
For planning and decision making on our standardization
activities.
To accomplish global understanding of design languages.
Future Plan
We will put the finishing touch to our BVDL.
We will use it for the coming 2010 fiscal year planning.
IEEE-DASC at SystemC Japan2010, 01Jul2010
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Copyright(C) JEITA 2008
JEITA
EDA-TC
: Japan Electronics and Information Technology Industries Association
( URL http://www.jeita.or.jp)
: EDA Technical Committee
( URL http://eda.ics.es.osaka-u.ac.jp/jeita/eda/index.html)
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