Transcript gerardin - Indico

Total Ionizing Dose Effects in
130-nm Commercial CMOS
Technologies for HEP experiments
L. Gonella, M. Silvestri, S. Gerardin
on behalf of the
DACEL – CERN collaboration
Outline
• Introduction & DACEL
• Experimental and Devices
• TID irradiation (X-rays):
– Core transistors:
• Worst-case bias conditions
– NMOSFETs
– PMOSFETs
• Impact of bias
• Different foundries
– I/O transistors:
• Worst-case bias conditions
– NMOSFETs
– PMOSFETs
• Impact of bias and foundry
• Conclusions
Perugia, 26/9/2006
S. Gerardin
DACEL
• Design And Characterization of deep submicron
ELectronic devices for future particle detectors
• Born in 2004
• Participating Institutions
– INFN sections:
• Bari
• Bologna
• Firenze
• Padova
• Torino
• In collaboration with CERN-MIC group
Perugia, 26/9/2006
S. Gerardin
Introduction
• Super LHC radiation environment
– Expected up to 100 Mrad in 10 years’ time
• Purpose of this work:
– Assess the suitability of commercial deep-submicron/
decananometer CMOS technologies for use in future
HEP experiments
Perugia, 26/9/2006
S. Gerardin
Devices
• MOSFETs manufactured in commercial 130-nm
CMOS technologies:
– Core transistors: tox=2.2nm
• Different aspect ratio (W\L)
• Enclosed Layout Transistors (ELT)
– I/O transistors: tox= 5.2nm
• Different aspect ratio
• Enclosed Layout Transistors (ELT)
• Three different suppliers called in the following: A,
B, and C
Perugia, 26/9/2006
S. Gerardin
Experimental
• CERN X-ray probe station
– X SEIFERT RP149 60-KV
maximum voltage, tungsten
target
– Dose rate: ~ 25 krad/s
– HP4145B parameter analyzer
– Thermal chuck (+5°C to +200°C)
– Custom probe card
– Switching matrix
– LabVIEW software
– Fully automated!
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S. Gerardin
Core Transistors:
Worst Case Bias Conditions
Perugia, 26/9/2006
S. Gerardin
Minimum Size NMOSFETs
-4
140
-5
120
10
-6
10
pre-rad
1 Mrad
5 Mrad
27 Mrad
97 Mrad
190 Mrad
Ids [A]
-7
10
-8
10
-9
10
-10
10
-11
10
Supplier A
Core
NMOSFET
(linear)
W/L=
0.16/0.12µm
100
Ids [A]
10
80
60
pre-rad
1 Mrad
5 Mrad
27 Mrad
97 Mrad
190 Mrad
40
20
-12
10
-0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
-0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
Vgs [V]
Vgs [V]
• Increase in off-current (Ileak) up to 3 orders of magnitude
• Large negative shift in the Vth
Source
• TID rebound in Vth and Ileak degradation
Gate
Drain
Perugia, 26/9/2006
S. Gerardin
Large-width NMOSFETs
Ids [A]
-3
10
-4
10
-5
10
pre-rad
-6
10
1 Mrad
-7
10
5 Mrad
-8
10
27 Mrad
-9
67 Mrad
10
-10
97 Mrad
10
-11
10
-12
10
-0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
Vgs [V]
Supplier A
Core NMOSFET (linear)
W/L= 2/0.12µm
Perugia, 26/9/2006
S. Gerardin
• Increase in off-current
(Ileak)
• No shift in the
threshold voltage
• TID rebound in the Ileak
degradation between 5
and 27 Mrad
Enclosed Layout NMOSFETs
Ids [mA]
-3
10
-4
10
-5
10
-6
10
-7
10
-8
10
pre-rad
-9
1 Mrad
10
97 Mrad
-10
10
190 Mrad
-11
10
-12
10
-0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
• Negligible TID effects
on Enclosed Layout
Transistors
• Very hard gate oxide!
(up to 190 Mrad)
Vgs [V]
Supplier A
Core ELT NMOSFET (enclosed)
W min, L=0.12µm
Perugia, 26/9/2006
S. Gerardin
Gate
Source
Drain
NMOSFETs: DVth vs dose
• Negligible TID effects
in large-width and
enclosed layout
NMOSFETs
0
-20
DVth [mV]
-40
-60
-80
-100
-120
-140
-160 5
10
6
10
7
10
8
10
9
10
TID [rad]
ELT
2/0.12
0.48/0.12
10/10
0.8/0.12
0.32/0.12
10/1
0.64/0.12
0.16/0.12
• TID rebound in the Vth
between 1 and 10Mrad
Supplier A
Linear Core NMOSFETs
Perugia, 26/9/2006
• Up to -150mV shift in
minimum size
NMOSFETs
(0.16/0.12m)
S. Gerardin
NMOSFETs: Ileak vs dose
• No change in ELTs
-7
10
• Up to 3 orders of
magnitude increase for
all W/L (non-ELT)
-8
Ileak [A]
10
-9
10
-10
10
pre-rad
5
10
ELT
2/0.12
0.48/0.12
6
7
10
10
TID [rad]
10/10
0.8/0.12
0.32/0.12
8
10
10
10/1
0.64/0.12
0.16/0.12
Supplier A
Core NMOSFETs
Perugia, 26/9/2006
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S. Gerardin
• TID rebound in the
degradation between 1
and 10 Mrad
Minimum Size PMOSFETs
40
-4
10
pre-rad
1 Mrad
5 Mrad
25 Mrad
55 Mrad
Supplier A
Core
PMOSFET
W/L=
0.16/0.12µm
Vds=1.5 V
-6
10
Ids [A]
-7
10
-8
10
-9
10
-10
10
-11
10
pre-rad
1 Mrad
5 Mrad
25 Mrad
55 Mrad
Ids [A]
-5
10
20
-12
10
-1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2
-1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2
Vgs [V]
Vgs [V]
• Less severe degradation compared to NMOSFETs
• Negative Vth shift
• Negligible changes in Ileak
Perugia, 26/9/2006
S. Gerardin
PMOSFETs: DVth vs dose
• Negligible effects in
large-width and
enclosed layout
NMOSFETs
50
40
DVth [mV]
30
20
10
0
-10
7
6
5
10
10
10
8
10
TID [rad]
10/10
0.8/0.12
10/1
0.48/0.12
2/0.12
0.16/0.12
Supplier A
Core PMOSFETs
Perugia, 26/9/2006
S. Gerardin
• Up to 50mV shift in
minimum size
MOSFETs
(0.16/0.12m)
STI: Achilles’ heel
positive trapped charge •
ELTs almost immune => Very hard
gate oxide due to scaling
Interface states
• Increase in Ileak in Large-Width and
Minimum-Size NMOSFETs =>
positive charge trapped in STI
poly gate
++
+
++
+
++
STI +
W
Parasitic Channels
Main Channel
Perugia, 26/9/2006
•
DVth larger in narrow channel
transistors (Radiation Induced
Narrow Channel Effect)
• TID rebound due to charge
trapping/interface generation kinetics:
maximum degradation between 1 and
10 Mrad
S. Gerardin
Core Transistors:
Impact of Bias Conditions
Perugia, 26/9/2006
S. Gerardin
Bias Dependence: DVth
Vgs=Vdd
0
Vgs=Vdd/2
-20
Vgs=0 V
DVth [mV]
-40
-60
-80
-100
-120
-140
-160 5
10
6
10
7
10
8
10
TID [rad]
Supplier A
Core NMOSFETs
W/L=0.16/0.12µm
Perugia, 26/9/2006
S. Gerardin
Minimum-Size NMOSFETs
• Worst condition:
– Vgs = Vdd
– DVth,max=-150 mV
• Intermediate condition
– Vgs = Vdd/2
– DVth.max=-120 mV
• Best condition
– Vgs = 0 V
– DVth,max=-60mV
Bias Dependence: Ileak
10
Vgs=Vdd
-6
Ileak [A]
Vgs=Vdd/2
10
-7
10
-8
10
-9
10
Vgs=0 V
-10
pre-rad
10
6
7
10
TID [rad]
10
8
Supplier A
Core NMOSFETs
W/L=0.16/0.12µm
Perugia, 26/9/2006
S. Gerardin
Minimum-Size NMOSFETs
• Worst condition:
– Vgs = Vdd
– Ileak,max ↑ = 103x
• Intermediate condition
– Vgs = Vdd/2
– Ileak,max ↑ = 102x
• Best condition
– Vgs = 0 V
– Ileak,max ↑ = 10x
Core Transistors:
Different Foundries
Perugia, 26/9/2006
S. Gerardin
Different foundries: NMOSFETs DVth
• Qualitatively, the same
effects
A 0.16/0.12
B 0.16/0.13
C 0.16/0.12
0
-20
DVth [mV]
-40
• Quantitatively, softer and
harder technologies
-60
-80
-100
• TID rebound occurs at
different total doses
-120
-140
-160 5
10
6
10
7
10
8
10
TID [rad]
Suppliers A,B,C
Core NMOSFETs
W/L=0.16/0.12-0.13µm
Perugia, 26/9/2006
S. Gerardin
9
10
• Maximum DVth in
minimum size
NMOSFETs from 50 mV
to 150 mV
Different foundries: NMOSFETs Ileak
• Qualitatively, the same
effects
-6
10
-7
Ileak [A]
10
• Quantitatively, softer and
harder technologies
-8
10
A 0.16/0.12
B 0.16/0.13
C 0.16/0.12
-9
10
-10
10
pre-rad
5
10
6
7
10
10
TID [rad]
• TID rebound occurs at
different total doses
8
10
Suppliers A,B,C
Core NMOSFETs
W/L=0.16/0.12-0.13µm
Perugia, 26/9/2006
S. Gerardin
9
10
• Maximum Ileak in minimum
size NMOSFETs from
10x to 104x
I/O Transistors:
Worst Case Bias Conditions
Perugia, 26/9/2006
S. Gerardin
Minimum Size NMOSFETs
Supplier A
I/O MOSFETs
W/L=
0.36/0.24µm
pre-rad
300 krad
1 Mrad
27 Mrad
97 Mrad
190 Mrad
0.4
0.8
1.2
1.6
2.0
-5
10
-6
10
-7
10
-8
10
-9
10
NMOSFET
-10
10
-11
PMOSFET
0.0
-4
10
Ids [A]
Ids [A]
-3
10
-4
10
-5
10
-6
10
-7
10
-8
10
-9
10
-10
10
-11
10
-12
10
2.4
Vgs [V]
10
pre-rad
1 Mrad
5 Mrad
25 Mrad
65 Mrad
-12
10
-2.4 -2.0 -1.6 -1.2 -0.8 -0.4
Vgs [V]
• More severe degradation compared to core devices for
NMOSFETs and PMOSFETs in terms of DVth and Ileak
• DVth and Ileak in NMOSFETs
• DVth in PMOSFETs
Perugia, 26/9/2006
S. Gerardin
0.0
Enclosed Layout
• ELTs degrade as
well
Ids [A]
-3
10
-4
10
-5
10
-6
10
-7
10
-8
10
-9
10
-10
10
-11
10
-12
10
pre-rad
1 Mrad
27 Mrad
97 Mrad
190 Mrad
0.0
0.4
0.8
1.2
1.6
2.0
Vgs [V]
Supplier A
I/O ELT NMOSFET
W min, L=0.12µm
Perugia, 26/9/2006
S. Gerardin
2.4
• Gate oxide still an
issue
• Increase in
subthreshold swing:
interface traps
NMOSFETs: DVth vs dose
•
100
DVth [mV]
0
-100
-200
DVth up to -400 mV
in minimum-size
devices
• TID rebound in
narrow devices
-300
-400
5
10
6
7
10
10
8
10
TID [rad]
0.36/0.24
2/0.24
ELT min/0.26
0.8/0.24
10/1
0.5/0.24
10/10
Supplier A
I/O NMOSFETs
Perugia, 26/9/2006
S. Gerardin
• Monotonic increase
in large-width and
ELTs
NMOSFETs: Ileak vs dose
• No change in ELTs
-5
10
-6
10
-7
10
• Up to 5 orders of
magnitude increase for
all W/L (non-ELTs)
Ileak [A]
-8
10
-9
10
-10
10
-11
10
pre-rad
5
6
10
10
10
TID [rad]
7
0.36/0.24
0.8/0.24
2/0.24
10/1
ELT W=min L=0.26
8
10
10
0.5/0.24
10/10
Supplier A
I/O NMOSFETs
Perugia, 26/9/2006
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• TID rebound in the
degradation between 1
and 10Mrad
PMOSFETs: DVth vs dose
•
400
DVth [mV]
300
200
DVth up to 350 mV in
minimum-size devices
• Smaller dependence on
geometry than
NMOSFETs
100
0
5
10
6
7
10
10
8
10
TID [rad]
10/10
10/1
0.8/0.24
0.5/0.24
ELT W=min, L=0.26
2/0.24
0.36/0.24
Supplier A
I/O PMOSFETs
Perugia, 26/9/2006
S. Gerardin
• Monotonic increase
Impact of Bias and Foundry
• Bias: dependence similar to that of core
transistors
– DVth.max(MS NMOSFETs) from -50 mV to -250 mV
– Ileak,max(NMOSFETs) ↑ from 10x to 105x
• Foundry: variability similar to that of core
transistors
– DVth,max(NMOSFETs) from -400 mV to -60 mV
– Ileak,max(NMOSFETs) ↑ from 102x to 108x
Perugia, 26/9/2006
S. Gerardin
Conclusions
• TID effects on Core Transistors
–
–
–
–
Narrow and short devices most affected
Very hard gate oxide, less hard STI
Large impact of bias conditions during operation
Large foundry to foundry variability
• TID effects on I/O Transistors
– Same effects as on Core Transistors + gate oxide still an issue
• 130-nm CMOS is harder than older technologies, and
may be up to the challenge of future HEP experiments
even without ELTs, but, in this case, needs constant
monitoring due to variability from foundry to foundry
Perugia, 26/9/2006
S. Gerardin
Open Issues
• Batch to batch variability (encouraging
preliminary results)
• Annealing and dose rate vs rebound
• Effects of different radiation sources (protons)
• Impact on flicker noise
• Long-term effects on the gate oxide reliability
Perugia, 26/9/2006
S. Gerardin