Transcript Switching Capacitance Using Buffers

Reducing Switching
Capacitance Using Buffers
Brad Hill
Dec. 6, 2005
ELEC6970-001 Class Presentation
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Objective
Reduce the Power of a Multiplier Circuit
 Do this with out Increasing the Delay of
the Critical Path

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Problem of Fanout

Fanout Increases the Capacitive Load on
the Driving Transistor


RC time constant increases due to increased
load capacitance
Delay of the circuit increases
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ELEC6970-001 Class Presentation
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Reasoning Behind Buffers

Single Fanout



There is a steady increase in transistor size
between stages
Extra Large Drive Transistors




The transistor driving the buffer now sees a single
fanout instead of a large fanout
Reduce Charging Resistance
Increase Drive Capacity
Lowers the RC time constant and speeds up the
switching to reduce delay
This does not directly reduce power but can be
used to our advantage
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ELEC6970-001 Class Presentation
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2x Buffer
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Multiplier
Simulated cells and circuits with multiple
cells compared results
 Found the best configuration of the buffers
in the circuits to reduce the delay

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Critical Path
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Cell with Buffers
• The fanout of both Sum_in and Carry_in in the Cell is 6
• These two signals benefit the most from buffers
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Delay of a Cell without Buffers (1.8V)
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Cell with Buffers (1.8V)
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Cell Delay (1.75V)
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Cell With Buffer Delay (1.75V)
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Comparison
Dynamic(W)
Static(W)
Delay(S)
Supply
Voltage
Single Cell
33.86u
171.14p
14.942p
1.8V
Cell with
buffers
35.08u
243.98p
-129.56p
1.8V
No Buffers
31.44u
162.10p
16.129p
1.75V
Buffers
32.34u
230.87p
-120.778p
1.75V
Difference
-1.52u
59.73p
-135.72
-0.05V
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ELEC6970-001 Class Presentation
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Two Cells with Buffers
• The two cells represent two cells in the middle of the multiplier
• A, B, B1, Sum_in, Carry_in, and Sum_in1 are driven for the simulation
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Cells 1.8V
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Cells no Buffers 1.75V
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Cells with Buffers 1.75V
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Two Cell Simulation Comparison
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Dynamic(
Static(W)
W)
Delay(S)
Supply
Voltage
No
Buffers
467.126u 342.282p
12.081p
1.8V
Buffers
488.136u
487.96p
-7.85p
1.8V
No
Buffers
418.677u
324.2060
p
13.510p
1.75V
Buffers
438.90u
461.75p
5.095p
1.75V
Differenc
e
-28.226u
119.552p
-6.986p
-0.05V
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Area of Cell
Dec. 6, 2005
Gate
Area
AO32
288
XOR
310
XNOR
282
NAND
88
Total
968
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Increase in Area

Area of a 2x Buffer


Area of Buffered Cell


84
1136
Percent Increase

17.36%
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Conclusions
Strategically placed buffers can greatly
decrease the delay of a circuit
 This reduction in delay can be used to
offset the increase in delay due to some
power reduction schemes

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