Transcript A NOC Design Methodology

Network on Chip
Architecture
Project Overview
Kari Tiensyrjä
VTT Electronics
Oulu, Finland
NOCARC project
Kari Tiensyrjä
EXSITE Workshop
Stockholm, Sweden, 22.11.2001
1
Outline
•
•
•
•
•
•
•
Capacity of Network on Chip in 2008
Research Hypothesis
Research Objective
“Applications” for NOC
Project Organisation
Publications and Dissemination
Conclusions
Kari Tiensyrjä
EXSITE Workshop
Stockholm, Sweden, 22.11.2001
2
Capacity of Network on Chip in 2008
10 computers
Average SoC design  1 million gates
1 billion transistors  250 million gates
1 NoC > 200 SoCs
1 GHz clock with RISC computer 
1000 MIPS performance
1 NOC capacity  100-10000 GIPS
Applicability of capacity is limited by
communication
10 computers
Kari Tiensyrjä
EXSITE Workshop
Stockholm, Sweden, 22.11.2001
3
Research Hypothesis
•
“Present generation, emerging design methods, tools, and the
associated chip architecture/platforms, while providing intermediate
solutions, will not survive when we reach the billion-transistor mark.
We propose a platform and methodology that will address these
factors and still allow companies to meet the time to market and
make profit.”
Kari Tiensyrjä
EXSITE Workshop
Stockholm, Sweden, 22.11.2001
4
Research Objective (1)
• Novel architecture template called network on chip, i.e. NOC for
future integrated telecommunication systems
NOC = Network of computation and storage
resources
NOC parameters:
Number of resources
Types of resources
GPU
DSP
Memory
Configurable HW
Coprocessors
Any combination
Communication capability
Kari Tiensyrjä
EXSITE Workshop
Stockholm, Sweden, 22.11.2001
5
Research Objective (2)
• Design methodology that supports definition of application
specific architecture, configuration of architecture and cooptimisation of both architecture and applications
Cores
Memories
Accelerators
Communication
structure
Generic backbone
Processors
and hardware
Product area specific platform
Code and
configuration
Definition of
NOC
platform
Optimised Virtual Components
“Application area specific IPR”
Algorithms
Applications
Features
Instantiation
of NoC
platform “Product specific IPR”
Optimised Intellectual Property
NoC system
Kari Tiensyrjä
EXSITE Workshop
Stockholm, Sweden, 22.11.2001
6
“Applications” for NOC
•
•
•
•
•
•
•
Multistandard terminal
Next generation base station
Simulation of human brain
Virtual reality creation
Telepresence
Holodeck (Star Trek)
Purpose of Life (Hitch Hikers Guide to
Galaxy)
• Simulation of universe
• Commercial operating system :-)
Kari Tiensyrjä
EXSITE Workshop
Stockholm, Sweden, 22.11.2001
Piece of cake
Realistic
applications
Maybe not even
for NOC
Real challenges
for every
archtitecture
7
Project Organisation
TEKES,
Academy
VINNOVA
EXSITEProgram
Ericsson,
Spirea
Nokia
NOCARC
Steering Group
Mx A
Mx B
NOCARC
Project Group
KTH
Mx C
VTT
Project in Figures
• 2001 - 2003
• ~€1000000
• ~10 person years
Further Information
• www.ele.kth.se/NOC/
• Kari Tiensyrjä, VTT,
<[email protected]>
• Axel Jantsch, KTH,
<[email protected]>
Mx D
Mx E
Kari Tiensyrjä
EXSITE Workshop
Stockholm, Sweden, 22.11.2001
8
Publications and Dissemination
1. A. Hemani, A. Jantsch, S. Kumar, A. Postula, J. Öberg, M. Millberg and D.
Lindqvist, "Network on chip: an architecture for billion transistor era",
Proceedings of NorChip 2000, November 6-7, Turku, Finland.
2. S. Kumar, M. Forsell, A. Hemani, A. Jantsch, M. Millberg, J.-P. Soininen, K.
Tiensyrjä, and J. Öberg, "Network on chip - a novel architecture
template for integrated telecommunication systems", NOCARC concept
paper draft version, August 13, 2001. 45 p.
3. Y. Zhang and K. Tiensyrjä, "Reconfigurable SOC Literature Survey" ,
NOCARC technical report, October 12, 2001. 44 p.
4. M. Forsell, "Optimal Pipeline Organization for General Purpose
Processors", Invited paper at SSGRR-2001 Conference, L'Aquila Italy,
August 6-12, 2001.
Kari Tiensyrjä
EXSITE Workshop
Stockholm, Sweden, 22.11.2001
9
Publications and Dissemination
5. M. Forsell and S. Kumar, "Virtual distributed shared memory for network
on chip", accepted at NORCHIP'2001 Conference, 12 - 13 November
2001, Kista, Sweden.
6. "Systems on Chip, Systems in Package" Workshop at ESSCIRC 2001,
27th European Solid-State Circuits Conference, 18 - 22 September 2001,
Villach, Austria. (Presentations: "Introduction" by Axel Jantsch,
"Physical Issues in NOCs" by Li-Rong Zheng, "Introduction to concepts
in parallel computing" by Martti Forsell, "NOC Architecture" by Axel
Jantsch and " A NOC Design Methodology" by Juha-Pekka Soininen).
7. M. Forsell, "Using parallel slackness for extracting ILP from sequential
threads", submitted to the Fourth International Conference on Massively
Parallel Computing Systems (MCPS 2002).
Kari Tiensyrjä
EXSITE Workshop
Stockholm, Sweden, 22.11.2001
10
Conclusions
Communication
channels
Non-configurable
hardware
NOC System
Product differentiation
Application
mapping
Architecture
Backbone design
Platform
System
does
not
exist
Resource development
Kari Tiensyrjä
– reuse in all levels is a
must
• Backbone, platform,
system based design
methodology approach
– provides variability and
performance
System Services
Operation principles
Product area specialisation
• Development of NOC
systems will be a huge
effort
• Analysis, decision,
estimation and
validation methods are
the cornerstones of
NOC development
EXSITE Workshop
Stockholm, Sweden, 22.11.2001
11